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-rw-r--r--techlibs/ecp5/synth_ecp5.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index d47b2bed4..463ddb5ca 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+ run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -322,11 +322,11 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap " + techmap_args);
if (abc9) {
- run("read_verilog -icells -lib +/ecp5/abc9_model.v");
+ run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
if (nowidelut)
- run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
+ run("abc9 -maxlut 4 -W 200");
else
- run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+ run("abc9 -W 200");
run("techmap -map +/ecp5/abc9_unmap.v");
} else {
if (nowidelut)