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-rw-r--r--techlibs/ice40/brams_map.v10
1 files changed, 4 insertions, 6 deletions
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index d022def7f..fcf431d2d 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -73,18 +73,16 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
if (MODE == 1) begin
assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]};
- assign B1DATA_16 = {B1DATA[7], B1DATA[7], B1DATA[6], B1DATA[6], B1DATA[5], B1DATA[5], B1DATA[4], B1DATA[4],
- B1DATA[3], B1DATA[3], B1DATA[2], B1DATA[2], B1DATA[1], B1DATA[1], B1DATA[0], B1DATA[0]};
+ assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
+ B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
end
if (MODE == 2) begin
assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
- assign B1DATA_16 = {B1DATA[3], B1DATA[3], B1DATA[3], B1DATA[3], B1DATA[2], B1DATA[2], B1DATA[2], B1DATA[2],
- B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0]};
+ assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
end
if (MODE == 3) begin
assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
- assign B1DATA_16 = {B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1],
- B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0]};
+ assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
end
endgenerate