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-rw-r--r--techlibs/ice40/cells_sim.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 58e067415..9c63336d7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -70,10 +70,10 @@ endmodule
// SiliconBlue Logic Cells
module SB_LUT4 (output O, input I0, I1, I2, I3);
- parameter [15:0] INIT = 0;
- wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
- wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
- wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
+ parameter [15:0] LUT_INIT = 0;
+ wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
+ wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule