1 files changed, 15 insertions, 15 deletions

diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index 29c999ff4..d7715135e 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -62,11 +62,11 @@ struct Ice40FfinitPass : public Pass {
 
 			for (auto wire : module->selected_wires())
 			{
-				if (wire->attributes.count("\\init") == 0)
+				if (wire->attributes.count(ID::init) == 0)
 					continue;
 
 				SigSpec wirebits = sigmap(wire);
-				Const initval = wire->attributes.at("\\init");
+				Const initval = wire->attributes.at(ID::init);
 				init_wires.insert(wire);
 
 				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
@@ -93,9 +93,9 @@ struct Ice40FfinitPass : public Pass {
 			}
 
 			pool<IdString> sb_dff_types = {
-				"\\SB_DFF",    "\\SB_DFFE",   "\\SB_DFFSR",   "\\SB_DFFR",   "\\SB_DFFSS",   "\\SB_DFFS",   "\\SB_DFFESR",
-				"\\SB_DFFER",  "\\SB_DFFESS", "\\SB_DFFES",   "\\SB_DFFN",   "\\SB_DFFNE",   "\\SB_DFFNSR", "\\SB_DFFNR",
-				"\\SB_DFFNSS", "\\SB_DFFNS",  "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES"
+				ID(SB_DFF),    ID(SB_DFFE),   ID(SB_DFFSR),   ID(SB_DFFR),   ID(SB_DFFSS),   ID(SB_DFFS),   ID(SB_DFFESR),
+				ID(SB_DFFER),  ID(SB_DFFESS), ID(SB_DFFES),   ID(SB_DFFN),   ID(SB_DFFNE),   ID(SB_DFFNSR), ID(SB_DFFNR),
+				ID(SB_DFFNSS), ID(SB_DFFNS),  ID(SB_DFFNESR), ID(SB_DFFNER), ID(SB_DFFNESS), ID(SB_DFFNES)
 			};
 
 			for (auto cell : module->selected_cells())
@@ -103,8 +103,8 @@ struct Ice40FfinitPass : public Pass {
 				if (!sb_dff_types.count(cell->type))
 					continue;
 
-				SigSpec sig_d = cell->getPort("\\D");
-				SigSpec sig_q = cell->getPort("\\Q");
+				SigSpec sig_d = cell->getPort(ID::D);
+				SigSpec sig_q = cell->getPort(ID::Q);
 
 				if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
 					continue;
@@ -133,14 +133,14 @@ struct Ice40FfinitPass : public Pass {
 				if (type_str.back() == 'S') {
 					type_str.back() = 'R';
 					cell->type = type_str;
-					cell->setPort("\\R", cell->getPort(ID::S));
+					cell->setPort(ID::R, cell->getPort(ID::S));
 					cell->unsetPort(ID::S);
 				} else
 				if (type_str.back() == 'R') {
 					type_str.back() = 'S';
 					cell->type = type_str;
-					cell->setPort(ID::S, cell->getPort("\\R"));
-					cell->unsetPort("\\R");
+					cell->setPort(ID::S, cell->getPort(ID::R));
+					cell->unsetPort(ID::R);
 				}
 
 				Wire *new_bit_d = module->addWire(NEW_ID);
@@ -149,17 +149,17 @@ struct Ice40FfinitPass : public Pass {
 				module->addNotGate(NEW_ID, bit_d, new_bit_d);
 				module->addNotGate(NEW_ID, new_bit_q, bit_q);
 
-				cell->setPort("\\D", new_bit_d);
-				cell->setPort("\\Q", new_bit_q);
+				cell->setPort(ID::D, new_bit_d);
+				cell->setPort(ID::Q, new_bit_q);
 			}
 
 			for (auto wire : init_wires)
 			{
-				if (wire->attributes.count("\\init") == 0)
+				if (wire->attributes.count(ID::init) == 0)
 					continue;
 
 				SigSpec wirebits = sigmap(wire);
-				Const &initval = wire->attributes.at("\\init");
+				Const &initval = wire->attributes.at(ID::init);
 				bool remove_attribute = true;
 
 				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
@@ -170,7 +170,7 @@ struct Ice40FfinitPass : public Pass {
 				}
 
 				if (remove_attribute)
-					wire->attributes.erase("\\init");
+					wire->attributes.erase(ID::init);
 			}
 		}
 	}