diff options
Diffstat (limited to 'techlibs/ice40/ice40_ffssr.cc')
| -rw-r--r-- | techlibs/ice40/ice40_ffssr.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index dae981618..ffb8c74b1 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -49,10 +49,10 @@ struct Ice40FfssrPass : public Pass { extra_args(args, argidx, design); pool<IdString> sb_dff_types; - sb_dff_types.insert("\\SB_DFF"); - sb_dff_types.insert("\\SB_DFFE"); - sb_dff_types.insert("\\SB_DFFN"); - sb_dff_types.insert("\\SB_DFFNE"); + sb_dff_types.insert(ID(SB_DFF)); + sb_dff_types.insert(ID(SB_DFFE)); + sb_dff_types.insert(ID(SB_DFFN)); + sb_dff_types.insert(ID(SB_DFFNE)); for (auto module : design->selected_modules()) { @@ -69,7 +69,7 @@ struct Ice40FfssrPass : public Pass { continue; } - if (cell->type != "$_MUX_") + if (cell->type != ID($_MUX_)) continue; SigBit bit_a = sigmap(cell->getPort(ID::A)); @@ -81,10 +81,10 @@ struct Ice40FfssrPass : public Pass { for (auto cell : ff_cells) { - if (cell->get_bool_attribute("\\dont_touch")) + if (cell->get_bool_attribute(ID(dont_touch))) continue; - SigSpec sig_d = cell->getPort("\\D"); + SigSpec sig_d = cell->getPort(ID::D); if (GetSize(sig_d) < 1) continue; @@ -117,11 +117,11 @@ struct Ice40FfssrPass : public Pass { if (sr_val == State::S1) { cell->type = cell->type.str() + "SS"; cell->setPort(ID::S, sr_sig); - cell->setPort("\\D", bit_d); + cell->setPort(ID::D, bit_d); } else { cell->type = cell->type.str() + "SR"; - cell->setPort("\\R", sr_sig); - cell->setPort("\\D", bit_d); + cell->setPort(ID::R, sr_sig); + cell->setPort(ID::D, bit_d); } } } |