6 files changed, 55 insertions, 4 deletions
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f..cd992bb24 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
new file mode 100644
index 000000000..d775efa78
--- /dev/null
+++ b/techlibs/ice40/cells.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
new file mode 100644
index 000000000..e2a54a42c
--- /dev/null
+++ b/techlibs/ice40/cells_box.v
@@ -0,0 +1,12 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,6 +881,7 @@ module SB_WARMBOOT (
 );
 endmodule
 
+(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
new file mode 100644
index 000000000..eef997869
--- /dev/null
+++ b/techlibs/ice40/lut.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8899bfcc4..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -92,13 +92,17 @@ struct SynthIce40Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -abc9\n");
+		log("        use abc9 instead of abc\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
 
-	string top_opt, blif_file, edif_file, json_file;
+
+	string top_opt, blif_file, edif_file, json_file, abc;
 	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
@@ -119,6 +123,7 @@ struct SynthIce40Pass : public ScriptPass
 		noabc = false;
 		abc2 = false;
 		vpr = false;
+		abc = "abc";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -201,6 +206,10 @@ struct SynthIce40Pass : public ScriptPass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-abc9") {
+				abc = "abc9";
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -274,7 +283,7 @@ struct SynthIce40Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
 
@@ -298,7 +307,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (check_label("map_luts"))
 		{
 			if (abc2 || help_mode) {
-				run("abc", "      (only if -abc2)");
+				run(abc, "      (only if -abc2)");
 				run("ice40_opt", "(only if -abc2)");
 			}
 			run("techmap -map +/ice40/latches_map.v");
@@ -307,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run("abc -dress -lut 4", "(skip if -noabc)");
+				if (abc == "abc9") {
+					run("read_verilog +/ice40/cells_box.v");
+					run("techmap -map +/techmap.v A:abc_box_id");
+					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run("blackbox A:abc_box_id");
+				}
+				else
+					run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {