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* ice40: Fix path delay definitionsStefan Riesenberger2023-03-101-14/+14
* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-2/+2
* Order ports with default assignments firstSean Anderson2022-08-091-10/+38
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-3/+19
* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-188-458/+293
* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-1/+1
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
* Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-084-4/+4
* Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+17
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
* verilog: significant block scoping improvementsZachary Snow2021-01-311-33/+40
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-304-142/+6
* ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-9/+9
* Use C++11 final/override keywords.whitequark2020-06-185-13/+13
* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+9
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-0/+153
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
* ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
* ice40: fix whitespaceEddie Hung2020-05-121-15/+14
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-8/+16
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-102-1/+63
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| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+1
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+59
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-024-75/+75
* | kernel: use more ID::*Eddie Hung2020-04-023-17/+17
* | Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
* | Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
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| * | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
* | | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
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* | ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
* | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
* | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
* | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-4/+22
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| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-4/+22
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* | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
* | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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