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-rw-r--r--techlibs/ice40/Makefile.inc11
-rw-r--r--techlibs/ice40/abc9_hx.box17
-rw-r--r--techlibs/ice40/abc9_hx.lut6
-rw-r--r--techlibs/ice40/abc9_lp.box17
-rw-r--r--techlibs/ice40/abc9_lp.lut6
-rw-r--r--techlibs/ice40/abc9_model.v29
-rw-r--r--techlibs/ice40/abc9_u.box17
-rw-r--r--techlibs/ice40/abc9_u.lut6
-rw-r--r--techlibs/ice40/arith_map.v27
-rw-r--r--techlibs/ice40/brams_map.v4
-rw-r--r--techlibs/ice40/cells_map.v17
-rw-r--r--techlibs/ice40/cells_sim.v1292
-rw-r--r--techlibs/ice40/dsp_map.v34
-rw-r--r--techlibs/ice40/ice40_braminit.cc159
-rw-r--r--techlibs/ice40/ice40_ffinit.cc14
-rw-r--r--techlibs/ice40/ice40_ffssr.cc7
-rw-r--r--techlibs/ice40/ice40_opt.cc123
-rw-r--r--techlibs/ice40/synth_ice40.cc224
-rw-r--r--techlibs/ice40/tests/.gitignore13
-rw-r--r--techlibs/ice40/tests/test_arith.ys9
-rw-r--r--techlibs/ice40/tests/test_dsp_map.sh107
-rw-r--r--techlibs/ice40/tests/test_dsp_model.sh16
-rw-r--r--techlibs/ice40/tests/test_dsp_model.v567
23 files changed, 2552 insertions, 170 deletions
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 14761c6c8..31478e80e 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -1,5 +1,6 @@
OBJS += techlibs/ice40/synth_ice40.o
+OBJS += techlibs/ice40/ice40_braminit.o
OBJS += techlibs/ice40/ice40_ffssr.o
OBJS += techlibs/ice40/ice40_ffinit.o
OBJS += techlibs/ice40/ice40_opt.o
@@ -13,7 +14,7 @@ EXTRA_OBJS += techlibs/ice40/brams_init.mk
techlibs/ice40/brams_init.mk: techlibs/ice40/brams_init.py
$(Q) mkdir -p techlibs/ice40
- $(P) python3 $<
+ $(P) $(PYTHON_EXECUTABLE) $<
$(Q) touch techlibs/ice40/brams_init.mk
techlibs/ice40/brams_init1.vh: techlibs/ice40/brams_init.mk
@@ -26,6 +27,14 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box
new file mode 100644
index 000000000..31e743669
--- /dev/null
+++ b/techlibs/ice40/abc9_hx.box
@@ -0,0 +1,17 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
+
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+400 379 449 316 316 # O
+259 231 - - 126 # CO
diff --git a/techlibs/ice40/abc9_hx.lut b/techlibs/ice40/abc9_hx.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/abc9_hx.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+# I3 I2 I1 I0
+1 1 316
+2 1 316 379
+3 1 316 379 400
+4 1 316 379 400 449
diff --git a/techlibs/ice40/abc9_lp.box b/techlibs/ice40/abc9_lp.box
new file mode 100644
index 000000000..71986a67b
--- /dev/null
+++ b/techlibs/ice40/abc9_lp.box
@@ -0,0 +1,17 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
+
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+589 558 661 465 465 # O
+675 609 - - 186 # CO
diff --git a/techlibs/ice40/abc9_lp.lut b/techlibs/ice40/abc9_lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/abc9_lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+# I3 I2 I1 I0
+1 1 465
+2 1 465 558
+3 1 465 558 589
+4 1 465 558 589 661
diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v
new file mode 100644
index 000000000..a5e5f4372
--- /dev/null
+++ b/techlibs/ice40/abc9_model.v
@@ -0,0 +1,29 @@
+(* abc9_box_id = 1, lib_whitebox *)
+module \$__ICE40_CARRY_WRAPPER (
+ (* abc9_carry *)
+ output CO,
+ output O,
+ input A, B,
+ (* abc9_carry *)
+ input CI,
+ input I0, I3
+);
+ parameter LUT = 0;
+ parameter I3_IS_CI = 0;
+ wire I3_OR_CI = I3_IS_CI ? CI : I3;
+ SB_CARRY carry (
+ .I0(A),
+ .I1(B),
+ .CI(CI),
+ .CO(CO)
+ );
+ SB_LUT4 #(
+ .LUT_INIT(LUT)
+ ) adder (
+ .I0(I0),
+ .I1(A),
+ .I2(B),
+ .I3(I3_OR_CI),
+ .O(O)
+ );
+endmodule
diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box
new file mode 100644
index 000000000..3d4b93834
--- /dev/null
+++ b/techlibs/ice40/abc9_u.box
@@ -0,0 +1,17 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
+
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+1231 1205 1285 874 874 # O
+675 609 - - 278 # CO
diff --git a/techlibs/ice40/abc9_u.lut b/techlibs/ice40/abc9_u.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/abc9_u.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+# I3 I2 I1 I0
+1 1 874
+2 1 874 1205
+3 1 874 1205 1231
+4 1 874 1205 1231 1285
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..ed4140e44 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,23 +44,20 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
- SB_CARRY carry (
- .I0(AA[i]),
- .I1(BB[i]),
+ \$__ICE40_CARRY_WRAPPER #(
+ // A[0]: 1010 1010 1010 1010
+ // A[1]: 1100 1100 1100 1100
+ // A[2]: 1111 0000 1111 0000
+ // A[3]: 1111 1111 0000 0000
+ .LUT(16'b 0110_1001_1001_0110),
+ .I3_IS_CI(1'b1)
+ ) carry (
+ .A(AA[i]),
+ .B(BB[i]),
.CI(C[i]),
- .CO(CO[i])
- );
- SB_LUT4 #(
- // I0: 1010 1010 1010 1010
- // I1: 1100 1100 1100 1100
- // I2: 1111 0000 1111 0000
- // I3: 1111 1111 0000 0000
- .LUT_INIT(16'b 0110_1001_1001_0110)
- ) adder (
.I0(1'b0),
- .I1(AA[i]),
- .I2(BB[i]),
- .I3(C[i]),
+ .I3(1'bx),
+ .CO(CO[i]),
.O(Y[i])
);
end endgenerate
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index 19a61d73b..ad3bccd21 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -7,8 +7,8 @@ module \$__ICE40_RAM4K (
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
- parameter integer READ_MODE = 0;
- parameter integer WRITE_MODE = 0;
+ parameter [1:0] READ_MODE = 0;
+ parameter [1:0] WRITE_MODE = 0;
parameter [0:0] NEGCLK_R = 0;
parameter [0:0] NEGCLK_W = 0;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0227ffadb..d5362eb83 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -27,6 +27,7 @@ module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (
module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
@@ -36,16 +37,19 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
- SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+ localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+ SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
end else
if (WIDTH == 2) begin
- SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+ localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
+ SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(1'b0), .I1(1'b0), .I2(A[0]), .I3(A[1]));
end else
if (WIDTH == 3) begin
- SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+ localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
+ SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(1'b0), .I1(A[0]), .I2(A[1]), .I3(A[2]));
end else
if (WIDTH == 4) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
@@ -55,3 +59,4 @@ module \$lut (A, Y);
end
endgenerate
endmodule
+`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 7778b5519..50eab5dde 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1,6 +1,10 @@
+`timescale 1ps / 1ps
+`define SB_DFF_REG reg Q = 0
+// `define SB_DFF_REG reg Q
-`define SB_DFF_REG reg Q = 0;
-// `define SB_DFF_REG reg Q;
+`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc9_arrival=TIME *) `endif
// SiliconBlue IO Cells
@@ -27,18 +31,27 @@ module SB_IO (
reg dout_q_0, dout_q_1;
reg outena_q;
+ // IO tile generates a constant 1'b1 internally if global_cen is not connected
+ wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
+ reg clken_pulled_ri;
+ reg clken_pulled_ro;
+
generate if (!NEG_TRIGGER) begin
- always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
- always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
- always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
- always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
- always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
+ always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
+ always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
+ always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
+ always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
+ always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
+ always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
+ always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
end else begin
- always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
- always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
- always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
- always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
- always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
+ always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
+ always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
+ always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
+ always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
+ always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
+ always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
+ always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
end endgenerate
always @* begin
@@ -68,6 +81,37 @@ module SB_IO (
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
endgenerate
`endif
+`ifdef TIMING
+specify
+ (INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0);
+ (INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0);
+ (PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0);
+ (OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0);
+ (D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0);
+ (OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0);
+
+ $setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
+ $setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
+ $setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
+ $setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
+ $setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
+ $setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
+ $setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
+ $setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
+ $setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
+ $setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
+endspecify
+`endif
endmodule
module SB_GB_IO (
@@ -114,10 +158,16 @@ module SB_GB (
output GLOBAL_BUFFER_OUTPUT
);
assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
+`ifdef TIMING
+specify
+ (USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0);
+endspecify
+`endif
endmodule
// SiliconBlue Logic Cells
+(* lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -126,27 +176,47 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
+(* lib_whitebox *)
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+
// Positive Edge SiliconBlue FF Cells
-module SB_DFF (output Q, input C, D);
- `SB_DFF_REG
+module SB_DFF (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, D
+);
always @(posedge C)
Q <= D;
endmodule
-module SB_DFFE (output Q, input C, E, D);
- `SB_DFF_REG
+module SB_DFFE (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, D
+);
always @(posedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFSR (output Q, input C, R, D);
- `SB_DFF_REG
+module SB_DFFSR (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(posedge C)
if (R)
Q <= 0;
@@ -154,8 +224,13 @@ module SB_DFFSR (output Q, input C, R, D);
Q <= D;
endmodule
-module SB_DFFR (output Q, input C, R, D);
- `SB_DFF_REG
+module SB_DFFR (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -163,8 +238,13 @@ module SB_DFFR (output Q, input C, R, D);
Q <= D;
endmodule
-module SB_DFFSS (output Q, input C, S, D);
- `SB_DFF_REG
+module SB_DFFSS (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(posedge C)
if (S)
Q <= 1;
@@ -172,8 +252,13 @@ module SB_DFFSS (output Q, input C, S, D);
Q <= D;
endmodule
-module SB_DFFS (output Q, input C, S, D);
- `SB_DFF_REG
+module SB_DFFS (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -181,8 +266,13 @@ module SB_DFFS (output Q, input C, S, D);
Q <= D;
endmodule
-module SB_DFFESR (output Q, input C, E, R, D);
- `SB_DFF_REG
+module SB_DFFESR (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(posedge C)
if (E) begin
if (R)
@@ -192,8 +282,13 @@ module SB_DFFESR (output Q, input C, E, R, D);
end
endmodule
-module SB_DFFER (output Q, input C, E, R, D);
- `SB_DFF_REG
+module SB_DFFER (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -201,8 +296,13 @@ module SB_DFFER (output Q, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFESS (output Q, input C, E, S, D);
- `SB_DFF_REG
+module SB_DFFESS (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(posedge C)
if (E) begin
if (S)
@@ -212,8 +312,13 @@ module SB_DFFESS (output Q, input C, E, S, D);
end
endmodule
-module SB_DFFES (output Q, input C, E, S, D);
- `SB_DFF_REG
+module SB_DFFES (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -223,21 +328,36 @@ endmodule
// Negative Edge SiliconBlue FF Cells
-module SB_DFFN (output Q, input C, D);
- `SB_DFF_REG
+module SB_DFFN (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, D
+);
always @(negedge C)
Q <= D;
endmodule
-module SB_DFFNE (output Q, input C, E, D);
- `SB_DFF_REG
+module SB_DFFNE (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, D
+);
always @(negedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFNSR (output Q, input C, R, D);
- `SB_DFF_REG
+module SB_DFFNSR (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(negedge C)
if (R)
Q <= 0;
@@ -245,8 +365,13 @@ module SB_DFFNSR (output Q, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNR (output Q, input C, R, D);
- `SB_DFF_REG
+module SB_DFFNR (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -254,8 +379,13 @@ module SB_DFFNR (output Q, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNSS (output Q, input C, S, D);
- `SB_DFF_REG
+module SB_DFFNSS (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(negedge C)
if (S)
Q <= 1;
@@ -263,8 +393,13 @@ module SB_DFFNSS (output Q, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNS (output Q, input C, S, D);
- `SB_DFF_REG
+module SB_DFFNS (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -272,8 +407,13 @@ module SB_DFFNS (output Q, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNESR (output Q, input C, E, R, D);
- `SB_DFF_REG
+module SB_DFFNESR (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(negedge C)
if (E) begin
if (R)
@@ -283,8 +423,13 @@ module SB_DFFNESR (output Q, input C, E, R, D);
end
endmodule
-module SB_DFFNER (output Q, input C, E, R, D);
- `SB_DFF_REG
+module SB_DFFNER (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -292,8 +437,13 @@ module SB_DFFNER (output Q, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFNESS (output Q, input C, E, S, D);
- `SB_DFF_REG
+module SB_DFFNESS (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(negedge C)
if (E) begin
if (S)
@@ -303,8 +453,13 @@ module SB_DFFNESS (output Q, input C, E, S, D);
end
endmodule
-module SB_DFFNES (output Q, input C, E, S, D);
- `SB_DFF_REG
+module SB_DFFNES (
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -315,6 +470,9 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -346,6 +504,8 @@ module SB_RAM40_4K (
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_FILE = "";
+
`ifndef BLACKBOX
wire [15:0] WMASK_I;
wire [15:0] RMASK_I;
@@ -428,24 +588,27 @@ module SB_RAM40_4K (
reg [15:0] memory [0:255];
initial begin
- for (i=0; i<16; i=i+1) begin
- memory[ 0*16 + i] <= INIT_0[16*i +: 16];
- memory[ 1*16 + i] <= INIT_1[16*i +: 16];
- memory[ 2*16 + i] <= INIT_2[16*i +: 16];
- memory[ 3*16 + i] <= INIT_3[16*i +: 16];
- memory[ 4*16 + i] <= INIT_4[16*i +: 16];
- memory[ 5*16 + i] <= INIT_5[16*i +: 16];
- memory[ 6*16 + i] <= INIT_6[16*i +: 16];
- memory[ 7*16 + i] <= INIT_7[16*i +: 16];
- memory[ 8*16 + i] <= INIT_8[16*i +: 16];
- memory[ 9*16 + i] <= INIT_9[16*i +: 16];
- memory[10*16 + i] <= INIT_A[16*i +: 16];
- memory[11*16 + i] <= INIT_B[16*i +: 16];
- memory[12*16 + i] <= INIT_C[16*i +: 16];
- memory[13*16 + i] <= INIT_D[16*i +: 16];
- memory[14*16 + i] <= INIT_E[16*i +: 16];
- memory[15*16 + i] <= INIT_F[16*i +: 16];
- end
+ if (INIT_FILE != "")
+ $readmemh(INIT_FILE, memory);
+ else
+ for (i=0; i<16; i=i+1) begin
+ memory[ 0*16 + i] = INIT_0[16*i +: 16];
+ memory[ 1*16 + i] = INIT_1[16*i +: 16];
+ memory[ 2*16 + i] = INIT_2[16*i +: 16];
+ memory[ 3*16 + i] = INIT_3[16*i +: 16];
+ memory[ 4*16 + i] = INIT_4[16*i +: 16];
+ memory[ 5*16 + i] = INIT_5[16*i +: 16];
+ memory[ 6*16 + i] = INIT_6[16*i +: 16];
+ memory[ 7*16 + i] = INIT_7[16*i +: 16];
+ memory[ 8*16 + i] = INIT_8[16*i +: 16];
+ memory[ 9*16 + i] = INIT_9[16*i +: 16];
+ memory[10*16 + i] = INIT_A[16*i +: 16];
+ memory[11*16 + i] = INIT_B[16*i +: 16];
+ memory[12*16 + i] = INIT_C[16*i +: 16];
+ memory[13*16 + i] = INIT_D[16*i +: 16];
+ memory[14*16 + i] = INIT_E[16*i +: 16];
+ memory[15*16 + i] = INIT_F[16*i +: 16];
+ end
end
always @(posedge WCLK) begin
@@ -478,6 +641,9 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -505,6 +671,8 @@ module SB_RAM40_4KNR (
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_FILE = "";
+
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
@@ -523,7 +691,8 @@ module SB_RAM40_4KNR (
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
- .INIT_F (INIT_F )
+ .INIT_F (INIT_F ),
+ .INIT_FILE (INIT_FILE )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
@@ -540,6 +709,9 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -567,6 +739,8 @@ module SB_RAM40_4KNW (
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_FILE = "";
+
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
@@ -585,7 +759,8 @@ module SB_RAM40_4KNW (
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
- .INIT_F (INIT_F )
+ .INIT_F (INIT_F ),
+ .INIT_FILE (INIT_FILE )
) RAM (
.RDATA(RDATA),
.RCLK (RCLK ),
@@ -602,6 +777,9 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -629,6 +807,8 @@ module SB_RAM40_4KNRNW (
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_FILE = "";
+
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
@@ -647,7 +827,8 @@ module SB_RAM40_4KNRNW (
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
- .INIT_F (INIT_F )
+ .INIT_F (INIT_F ),
+ .INIT_FILE (INIT_FILE )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
@@ -667,7 +848,12 @@ endmodule
module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
- output LO, O, COUT
+ output LO,
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
+ output O,
+ output COUT
);
parameter [15:0] LUT_INIT = 0;
@@ -677,31 +863,84 @@ module ICESTORM_LC (
parameter [0:0] SET_NORESET = 0;
parameter [0:0] ASYNC_SR = 0;
- wire COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx;
+ parameter [0:0] CIN_CONST = 0;
+ parameter [0:0] CIN_SET = 0;
+
+ wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0;
+ wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1;
+ wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2;
+ wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3;
+ wire SR_pd = (SR === 1'bz) ? 1'b0 : SR;
+ wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN;
+
+ wire mux_cin = CIN_CONST ? CIN_SET : CIN;
+
+ assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx;
- wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
- wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
- wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
- wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
+ wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0];
+ wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0];
+ wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0];
+ wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0];
assign LO = lut_o;
wire polarized_clk;
assign polarized_clk = CLK ^ NEG_CLK;
- reg o_reg;
+ reg o_reg = 1'b0;
always @(posedge polarized_clk)
- if (CEN)
- o_reg <= SR ? SET_NORESET : lut_o;
+ if (CEN_pu)
+ o_reg <= SR_pd ? SET_NORESET : lut_o;
- reg o_reg_async;
+ reg o_reg_async = 1'b0;
always @(posedge polarized_clk, posedge SR)
- if (SR)
- o_reg <= SET_NORESET;
- else if (CEN)
- o_reg <= lut_o;
+ if (SR_pd)
+ o_reg_async <= SET_NORESET;
+ else if (CEN_pu)
+ o_reg_async <= lut_o;
assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
+`ifdef TIMING
+specify
+ (I0 => O) = (0:0:0, 0:0:0);
+ (I1 => O) = (0:0:0, 0:0:0);
+ (I2 => O) = (0:0:0, 0:0:0);
+ (I3 => O) = (0:0:0, 0:0:0);
+ (I0 => LO) = (0:0:0, 0:0:0);
+ (I1 => LO) = (0:0:0, 0:0:0);
+ (I2 => LO) = (0:0:0, 0:0:0);
+ (I3 => LO) = (0:0:0, 0:0:0);
+ (I1 => COUT) = (0:0:0, 0:0:0);
+ (I2 => COUT) = (0:0:0, 0:0:0);
+ (CIN => COUT) = (0:0:0, 0:0:0);
+ (CLK => O) = (0:0:0, 0:0:0);
+ (SR => O) = (0:0:0, 0:0:0);
+ $setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0);
+ $setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0);
+ $setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
+endspecify
+`endif
endmodule
// SiliconBlue PLL Cells
@@ -881,3 +1120,882 @@ module SB_WARMBOOT (
input S0
);
endmodule
+
+module SB_SPRAM256KA (
+ input [13:0] ADDRESS,
+ input [15:0] DATAIN,
+ input [3:0] MASKWREN,
+ input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
+ `ABC9_ARRIVAL_U(1821) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207
+ output reg [15:0] DATAOUT
+);
+`ifndef BLACKBOX
+`ifndef EQUIV
+ reg [15:0] mem [0:16383];
+ wire off = SLEEP || !POWEROFF;
+ integer i;
+
+ always @(negedge POWEROFF) begin
+ for (i = 0; i <= 16383; i = i+1)
+ mem[i] = 'bx;
+ end
+
+ always @(posedge CLOCK, posedge off) begin
+ if (off) begin
+ DATAOUT <= 0;
+ end else
+ if (CHIPSELECT && !STANDBY && !WREN) begin
+ DATAOUT <= mem[ADDRESS];
+ end else begin
+ if (CHIPSELECT && !STANDBY && WREN) begin
+ if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
+ if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
+ if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
+ if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
+ end
+ DATAOUT <= 'bx;
+ end
+ end
+`endif
+`endif
+endmodule
+
+(* blackbox *)
+module SB_HFOSC(
+ input TRIM0,
+ input TRIM1,
+ input TRIM2,
+ input TRIM3,
+ input TRIM4,
+ input TRIM5,
+ input TRIM6,
+ input TRIM7,
+ input TRIM8,
+ input TRIM9,
+ input CLKHFPU,
+ input CLKHFEN,
+ output CLKHF
+);
+parameter TRIM_EN = "0b0";
+parameter CLKHF_DIV = "0b00";
+endmodule
+
+(* blackbox *)
+module SB_LFOSC(
+ input CLKLFPU,
+ input CLKLFEN,
+ output CLKLF
+);
+endmodule
+
+(* blackbox *)
+module SB_RGBA_DRV(
+ input CURREN,
+ input RGBLEDEN,
+ input RGB0PWM,
+ input RGB1PWM,
+ input RGB2PWM,
+ output RGB0,
+ output RGB1,
+ output RGB2
+);
+parameter CURRENT_MODE = "0b0";
+parameter RGB0_CURRENT = "0b000000";
+parameter RGB1_CURRENT = "0b000000";
+parameter RGB2_CURRENT = "0b000000";
+endmodule
+
+(* blackbox *)
+module SB_LED_DRV_CUR(
+ input EN,
+ output LEDPU
+);
+endmodule
+
+(* blackbox *)
+module SB_RGB_DRV(
+ input RGBLEDEN,
+ input RGB0PWM,
+ input RGB1PWM,
+ input RGB2PWM,
+ input RGBPU,
+ output RGB0,
+ output RGB1,
+ output RGB2
+);
+parameter CURRENT_MODE = "0b0";
+parameter RGB0_CURRENT = "0b000000";
+parameter RGB1_CURRENT = "0b000000";
+parameter RGB2_CURRENT = "0b000000";
+endmodule
+
+(* blackbox *)
+module SB_I2C(
+ input SBCLKI,
+ input SBRWI,
+ input SBSTBI,
+ input SBADRI7,
+ input SBADRI6,
+ input SBADRI5,
+ input SBADRI4,
+ input SBADRI3,
+ input SBADRI2,
+ input SBADRI1,
+ input SBADRI0,
+ input SBDATI7,
+ input SBDATI6,
+ input SBDATI5,
+ input SBDATI4,
+ input SBDATI3,
+ input SBDATI2,
+ input SBDATI1,
+ input SBDATI0,
+ input SCLI,
+ input SDAI,
+ output SBDATO7,
+ output SBDATO6,
+ output SBDATO5,
+ output SBDATO4,
+ output SBDATO3,
+ output SBDATO2,
+ output SBDATO1,
+ output SBDATO0,
+ output SBACKO,
+ output I2CIRQ,
+ output I2CWKUP,
+ output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
+ output SCLOE,
+ output SDAO,
+ output SDAOE
+);
+parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
+parameter BUS_ADDR74 = "0b0001";
+endmodule
+
+(* blackbox *)
+module SB_SPI (
+ input SBCLKI,
+ input SBRWI,
+ input SBSTBI,
+ input SBADRI7,
+ input SBADRI6,
+ input SBADRI5,
+ input SBADRI4,
+ input SBADRI3,
+ input SBADRI2,
+ input SBADRI1,
+ input SBADRI0,
+ input SBDATI7,
+ input SBDATI6,
+ input SBDATI5,
+ input SBDATI4,
+ input SBDATI3,
+ input SBDATI2,
+ input SBDATI1,
+ input SBDATI0,
+ input MI,
+ input SI,
+ input SCKI,
+ input SCSNI,
+ output SBDATO7,
+ output SBDATO6,
+ output SBDATO5,
+ output SBDATO4,
+ output SBDATO3,
+ output SBDATO2,
+ output SBDATO1,
+ output SBDATO0,
+ output SBACKO,
+ output SPIIRQ,
+ output SPIWKUP,
+ output SO,
+ output SOE,
+ output MO,
+ output MOE,
+ output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
+ output SCKOE,
+ output MCSNO3,
+ output MCSNO2,
+ output MCSNO1,
+ output MCSNO0,
+ output MCSNOE3,
+ output MCSNOE2,
+ output MCSNOE1,
+ output MCSNOE0
+);
+parameter BUS_ADDR74 = "0b0000";
+endmodule
+
+(* blackbox *)
+module SB_LEDDA_IP(
+ input LEDDCS,
+ input LEDDCLK,
+ input LEDDDAT7,
+ input LEDDDAT6,
+ input LEDDDAT5,
+ input LEDDDAT4,
+ input LEDDDAT3,
+ input LEDDDAT2,
+ input LEDDDAT1,
+ input LEDDDAT0,
+ input LEDDADDR3,
+ input LEDDADDR2,
+ input LEDDADDR1,
+ input LEDDADDR0,
+ input LEDDDEN,
+ input LEDDEXE,
+ input LEDDRST,
+ output PWMOUT0,
+ output PWMOUT1,
+ output PWMOUT2,
+ output LEDDON
+);
+endmodule
+
+(* blackbox *)
+module SB_FILTER_50NS(
+ input FILTERIN,
+ output FILTEROUT
+);
+endmodule
+
+module SB_IO_I3C (
+ inout PACKAGE_PIN,
+ input LATCH_INPUT_VALUE,
+ input CLOCK_ENABLE,
+ input INPUT_CLK,
+ input OUTPUT_CLK,
+ input OUTPUT_ENABLE,
+ input D_OUT_0,
+ input D_OUT_1,
+ output D_IN_0,
+ output D_IN_1,
+ input PU_ENB,
+ input WEAK_PU_ENB
+);
+ parameter [5:0] PIN_TYPE = 6'b000000;
+ parameter [0:0] PULLUP = 1'b0;
+ parameter [0:0] WEAK_PULLUP = 1'b0;
+ parameter [0:0] NEG_TRIGGER = 1'b0;
+ parameter IO_STANDARD = "SB_LVCMOS";
+
+`ifndef BLACKBOX
+ reg dout, din_0, din_1;
+ reg din_q_0, din_q_1;
+ reg dout_q_0, dout_q_1;
+ reg outena_q;
+
+ generate if (!NEG_TRIGGER) begin
+ always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
+ always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
+ always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
+ always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
+ always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
+ end else begin
+ always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
+ always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
+ always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
+ always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
+ always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
+ end endgenerate
+
+ always @* begin
+ if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
+ din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
+ din_1 = din_q_1;
+ end
+
+ // work around simulation glitches on dout in DDR mode
+ reg outclk_delayed_1;
+ reg outclk_delayed_2;
+ always @* outclk_delayed_1 <= OUTPUT_CLK;
+ always @* outclk_delayed_2 <= outclk_delayed_1;
+
+ always @* begin
+ if (PIN_TYPE[3])
+ dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
+ else
+ dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
+ end
+
+ assign D_IN_0 = din_0, D_IN_1 = din_1;
+
+ generate
+ if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
+ if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
+ if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
+ endgenerate
+`endif
+endmodule
+
+module SB_IO_OD (
+ inout PACKAGEPIN,
+ input LATCHINPUTVALUE,
+ input CLOCKENABLE,
+ input INPUTCLK,
+ input OUTPUTCLK,
+ input OUTPUTENABLE,
+ input DOUT1,
+ input DOUT0,
+ output DIN1,
+ output DIN0
+);
+ parameter [5:0] PIN_TYPE = 6'b000000;
+ parameter [0:0] NEG_TRIGGER = 1'b0;
+
+`ifndef BLACKBOX
+ reg dout, din_0, din_1;
+ reg din_q_0, din_q_1;
+ reg dout_q_0, dout_q_1;
+ reg outena_q;
+
+ generate if (!NEG_TRIGGER) begin
+ always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
+ always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
+ always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
+ always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
+ always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
+ end else begin
+ always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
+ always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
+ always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
+ always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
+ always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
+ end endgenerate
+
+ always @* begin
+ if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
+ din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
+ din_1 = din_q_1;
+ end
+
+ // work around simulation glitches on dout in DDR mode
+ reg outclk_delayed_1;
+ reg outclk_delayed_2;
+ always @* outclk_delayed_1 <= OUTPUTCLK;
+ always @* outclk_delayed_2 <= outclk_delayed_1;
+
+ always @* begin
+ if (PIN_TYPE[3])
+ dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
+ else
+ dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
+ end
+
+ assign DIN0 = din_0, DIN1 = din_1;
+
+ generate
+ if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
+ if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
+ if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
+ endgenerate
+`endif
+endmodule
+
+module SB_MAC16 (
+ input CLK, CE,
+ input [15:0] C, A, B, D,
+ input AHOLD, BHOLD, CHOLD, DHOLD,
+ input IRSTTOP, IRSTBOT,
+ input ORSTTOP, ORSTBOT,
+ input OLOADTOP, OLOADBOT,
+ input ADDSUBTOP, ADDSUBBOT,
+ input OHOLDTOP, OHOLDBOT,
+ input CI, ACCUMCI, SIGNEXTIN,
+ output [31:0] O,
+ output CO, ACCUMCO, SIGNEXTOUT
+);
+ parameter [0:0] NEG_TRIGGER = 0;
+ parameter [0:0] C_REG = 0;
+ parameter [0:0] A_REG = 0;
+ parameter [0:0] B_REG = 0;
+ parameter [0:0] D_REG = 0;
+ parameter [0:0] TOP_8x8_MULT_REG = 0;
+ parameter [0:0] BOT_8x8_MULT_REG = 0;
+ parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
+ parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
+ parameter [1:0] TOPOUTPUT_SELECT = 0;
+ parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
+ parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
+ parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
+ parameter [1:0] BOTOUTPUT_SELECT = 0;
+ parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
+ parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
+ parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
+ parameter [0:0] MODE_8x8 = 0;
+ parameter [0:0] A_SIGNED = 0;
+ parameter [0:0] B_SIGNED = 0;
+
+ wire clock = CLK ^ NEG_TRIGGER;
+
+ // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
+ // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
+ // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
+ wire [15:0] iA, iB, iC, iD;
+ wire [15:0] iF, iJ, iK, iG;
+ wire [31:0] iL, iH;
+ wire [15:0] iW, iX, iP, iQ;
+ wire [15:0] iY, iZ, iR, iS;
+ wire HCI, LCI, LCO;
+
+ // Regs C and A
+ reg [15:0] rC, rA;
+ always @(posedge clock, posedge IRSTTOP) begin
+ if (IRSTTOP) begin
+ rC <= 0;
+ rA <= 0;
+ end else if (CE) begin
+ if (!CHOLD) rC <= C;
+ if (!AHOLD) rA <= A;
+ end
+ end
+ assign iC = C_REG ? rC : C;
+ assign iA = A_REG ? rA : A;
+
+ // Regs B and D
+ reg [15:0] rB, rD;
+ always @(posedge clock, posedge IRSTBOT) begin
+ if (IRSTBOT) begin
+ rB <= 0;
+ rD <= 0;
+ end else if (CE) begin
+ if (!BHOLD) rB <= B;
+ if (!DHOLD) rD <= D;
+ end
+ end
+ assign iB = B_REG ? rB : B;
+ assign iD = D_REG ? rD : D;
+
+ // Multiplier Stage
+ wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
+ wire [15:0] Ah, Al, Bh, Bl;
+ assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
+ assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+ assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
+ assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
+ assign p_Ah_Bh = Ah * Bh; // F
+ assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
+ assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
+ assign p_Al_Bl = Al * Bl; // G
+
+ // Regs F and J
+ reg [15:0] rF, rJ;
+ always @(posedge clock, posedge IRSTTOP) begin
+ if (IRSTTOP) begin
+ rF <= 0;
+ rJ <= 0;
+ end else if (CE) begin
+ rF <= p_Ah_Bh;
+ if (!MODE_8x8) rJ <= p_Al_Bh;
+ end
+ end
+ assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
+ assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
+
+ // Regs K and G
+ reg [15:0] rK, rG;
+ always @(posedge clock, posedge IRSTBOT) begin
+ if (IRSTBOT) begin
+ rK <= 0;
+ rG <= 0;
+ end else if (CE) begin
+ if (!MODE_8x8) rK <= p_Ah_Bl;
+ rG <= p_Al_Bl;
+ end
+ end
+ assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
+ assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
+
+ // Adder Stage
+ wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
+ wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
+ assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
+
+ // Reg H
+ reg [31:0] rH;
+ always @(posedge clock, posedge IRSTBOT) begin
+ if (IRSTBOT) begin
+ rH <= 0;
+ end else if (CE) begin
+ if (!MODE_8x8) rH <= iL;
+ end
+ end
+ assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
+
+ // Hi Output Stage
+ wire [15:0] XW, Oh;
+ reg [15:0] rQ;
+ assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
+ assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
+ assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
+ assign CO = ACCUMCO ^ ADDSUBTOP;
+ assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
+ always @(posedge clock, posedge ORSTTOP) begin
+ if (ORSTTOP) begin
+ rQ <= 0;
+ end else if (CE) begin
+ if (!OHOLDTOP) rQ <= iP;
+ end
+ end
+ assign iQ = rQ;
+ assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
+ assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
+ assign SIGNEXTOUT = iX[15];
+
+ // Lo Output Stage
+ wire [15:0] YZ, Ol;
+ reg [15:0] rS;
+ assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
+ assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
+ assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
+ assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
+ always @(posedge clock, posedge ORSTBOT) begin
+ if (ORSTBOT) begin
+ rS <= 0;
+ end else if (CE) begin
+ if (!OHOLDBOT) rS <= iR;
+ end
+ end
+ assign iS = rS;
+ assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
+ assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
+ assign O = {Oh, Ol};
+endmodule
+
+// Post-place-and-route RAM model
+module ICESTORM_RAM(
+ output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0,
+ input RCLK, RCLKE, RE,
+ input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0,
+ input WCLK, WCLKE, WE,
+ input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0,
+ input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0,
+ input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0
+);
+ parameter WRITE_MODE = 0;
+ parameter READ_MODE = 0;
+
+ parameter NEG_CLK_R = 1'b0;
+ parameter NEG_CLK_W = 1'b0;
+
+ parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+ // Pull-down and pull-up functions
+ function pd;
+ input x;
+ begin
+ pd = (x === 1'bz) ? 1'b0 : x;
+ end
+ endfunction
+
+ function pu;
+ input x;
+ begin
+ pu = (x === 1'bz) ? 1'b1 : x;
+ end
+ endfunction
+
+ SB_RAM40_4K #(
+ .WRITE_MODE(WRITE_MODE),
+ .READ_MODE (READ_MODE ),
+ .INIT_0 (INIT_0 ),
+ .INIT_1 (INIT_1 ),
+ .INIT_2 (INIT_2 ),
+ .INIT_3 (INIT_3 ),
+ .INIT_4 (INIT_4 ),
+ .INIT_5 (INIT_5 ),
+ .INIT_6 (INIT_6 ),
+ .INIT_7 (INIT_7 ),
+ .INIT_8 (INIT_8 ),
+ .INIT_9 (INIT_9 ),
+ .INIT_A (INIT_A ),
+ .INIT_B (INIT_B ),
+ .INIT_C (INIT_C ),
+ .INIT_D (INIT_D ),
+ .INIT_E (INIT_E ),
+ .INIT_F (INIT_F )
+ ) RAM (
+ .RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}),
+ .RCLK (pd(RCLK) ^ NEG_CLK_R),
+ .RCLKE(pu(RCLKE)),
+ .RE (pd(RE)),
+ .RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}),
+ .WCLK (pd(WCLK) ^ NEG_CLK_W),
+ .WCLKE(pu(WCLKE)),
+ .WE (pd(WE)),
+ .WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}),
+ .MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8),
+ pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}),
+ .WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8),
+ pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)})
+ );
+
+`ifdef TIMING
+specify
+ (RCLK => RDATA_15) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_14) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_13) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_12) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_11) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_10) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_9) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_8) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_7) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_6) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_5) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_4) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_3) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_2) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_1) = (0:0:0, 0:0:0);
+ (RCLK => RDATA_0) = (0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
+ $setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
+ $setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
+ $setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
+ $setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
+
+endspecify
+`endif
+endmodule
diff --git a/techlibs/ice40/dsp_map.v b/techlibs/ice40/dsp_map.v
new file mode 100644
index 000000000..06fa73956
--- /dev/null
+++ b/techlibs/ice40/dsp_map.v
@@ -0,0 +1,34 @@
+module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 0;
+ parameter B_WIDTH = 0;
+ parameter Y_WIDTH = 0;
+
+ SB_MAC16 #(
+ .NEG_TRIGGER(1'b0),
+ .C_REG(1'b0),
+ .A_REG(1'b0),
+ .B_REG(1'b0),
+ .D_REG(1'b0),
+ .TOP_8x8_MULT_REG(1'b0),
+ .BOT_8x8_MULT_REG(1'b0),
+ .PIPELINE_16x16_MULT_REG1(1'b0),
+ .PIPELINE_16x16_MULT_REG2(1'b0),
+ .TOPOUTPUT_SELECT(2'b11),
+ .TOPADDSUB_LOWERINPUT(2'b0),
+ .TOPADDSUB_UPPERINPUT(1'b0),
+ .TOPADDSUB_CARRYSELECT(2'b0),
+ .BOTOUTPUT_SELECT(2'b11),
+ .BOTADDSUB_LOWERINPUT(2'b0),
+ .BOTADDSUB_UPPERINPUT(1'b0),
+ .BOTADDSUB_CARRYSELECT(2'b0),
+ .MODE_8x8(1'b0),
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED)
+ ) _TECHMAP_REPLACE_ (
+ .A(A),
+ .B(B),
+ .O(Y),
+ );
+endmodule
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
new file mode 100644
index 000000000..1a139ffea
--- /dev/null
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -0,0 +1,159 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+#include <bitset>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void run_ice40_braminit(Module *module)
+{
+ for (auto cell : module->selected_cells())
+ {
+ uint16_t mem[256];
+
+ /* Only consider cells we're interested in */
+ if (cell->type != "\\SB_RAM40_4K" &&
+ cell->type != "\\SB_RAM40_4KNR" &&
+ cell->type != "\\SB_RAM40_4KNW" &&
+ cell->type != "\\SB_RAM40_4KNRNW")
+ continue;
+ if (!cell->hasParam("\\INIT_FILE"))
+ continue;
+ std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
+ cell->unsetParam("\\INIT_FILE");
+ if (init_file == "")
+ continue;
+
+ /* Open file */
+ log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str());
+
+ std::ifstream f;
+ f.open(init_file.c_str());
+ if (f.fail()) {
+ log("Can not open file `%s`.\n", init_file.c_str());
+ continue;
+ }
+
+ /* Defaults to 0 */
+ memset(mem, 0x00, sizeof(mem));
+
+ /* Process each line */
+ bool in_comment = false;
+ int cursor = 0;
+
+ while (!f.eof())
+ {
+ std::string line, token;
+ std::getline(f, line);
+
+ for (int i = 0; i < GetSize(line); i++)
+ {
+ if (in_comment && line.compare(i, 2, "*/") == 0) {
+ line[i] = ' ';
+ line[i+1] = ' ';
+ in_comment = false;
+ continue;
+ }
+ if (!in_comment && line.compare(i, 2, "/*") == 0)
+ in_comment = true;
+ if (in_comment)
+ line[i] = ' ';
+ }
+
+ while (1)
+ {
+ bool set_cursor = false;
+ long value;
+
+ token = next_token(line, " \t\r\n");
+ if (token.empty() || token.compare(0, 2, "//") == 0)
+ break;
+
+ if (token[0] == '@') {
+ token = token.substr(1);
+ set_cursor = true;
+ }
+
+ const char *nptr = token.c_str();
+ char *endptr;
+ value = strtol(nptr, &endptr, 16);
+ if (!*nptr || *endptr) {
+ log("Can not parse %s `%s` for %s.\n",
+ set_cursor ? "address" : "value",
+ nptr, token.c_str()
+ );
+ continue;
+ }
+
+ if (set_cursor)
+ cursor = value;
+ else if (cursor >= 0 && cursor < 256)
+ mem[cursor++] = value;
+ else
+ log("Attempt to initialize non existent address %d\n", cursor);
+ }
+ }
+
+ /* Set attributes */
+ const char *hex = "0123456789ABCDEF";
+ for (int i=0; i<16; i++) {
+ std::string val = "";
+ for (int j=15; j>=0; j--)
+ val += std::bitset<16>(mem[i*16+j]).to_string();
+ cell->setParam("\\INIT_" + std::string(1, hex[i]), RTLIL::Const::from_string(val));
+ }
+ }
+}
+
+struct Ice40BRAMInitPass : public Pass {
+ Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" ice40_braminit\n");
+ log("\n");
+ log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
+ log("parameter and converts it into the required INIT_x attributes\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing ICE40_BRAMINIT pass.\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ // if (args[argidx] == "-???") {
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ run_ice40_braminit(module);
+ }
+} Ice40BRAMInitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index c914b20e8..c098736e9 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfinitPass : public Pass {
Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass {
log("nonzero init values.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");
@@ -78,10 +78,12 @@ struct Ice40FfinitPass : public Pass {
continue;
if (initbits.count(bit)) {
- if (initbits.at(bit) != val)
- log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+ if (initbits.at(bit) != val) {
+ log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+ initbits.at(bit) = State::Sx;
+ }
continue;
}
@@ -114,6 +116,10 @@ struct Ice40FfinitPass : public Pass {
continue;
State val = initbits.at(bit_q);
+
+ if (val == State::Sx)
+ continue;
+
handled_initbits.insert(bit_q);
log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 9afbc0fce..a7649d7a0 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfssrPass : public Pass {
Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
log("\n");
log(" ice40_ffssr [options] [selection]\n");
@@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass {
log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
@@ -81,6 +81,9 @@ struct Ice40FfssrPass : public Pass {
for (auto cell : ff_cells)
{
+ if (cell->get_bool_attribute("\\dont_touch"))
+ continue;
+
SigSpec sig_d = cell->getPort("\\D");
if (GetSize(sig_d) < 1)
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index ae72f5d64..925ab31bb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -26,7 +26,14 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-static void run_ice40_opts(Module *module, bool unlut_mode)
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+ if (GetSize(sig) == 0)
+ return State::S0;
+ return sig[0];
+}
+
+static void run_ice40_opts(Module *module)
{
pool<SigBit> optimized_co;
vector<Cell*> sb_lut_cells;
@@ -34,6 +41,11 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
for (auto cell : module->selected_cells())
{
+ if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER"))
+ continue;
+ if (cell->has_keep_attr())
+ continue;
+
if (cell->type == "\\SB_LUT4")
{
sb_lut_cells.push_back(cell);
@@ -45,7 +57,11 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
- SigBit inbit[3] = {cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\CI")};
+ SigBit inbit[3] = {
+ get_bit_or_zero(cell->getPort("\\I0")),
+ get_bit_or_zero(cell->getPort("\\I1")),
+ get_bit_or_zero(cell->getPort("\\CI"))
+ };
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
if (inbit[i] == State::S1)
@@ -63,8 +79,8 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
- optimized_co.insert(sigmap(cell->getPort("\\CO")));
- module->connect(cell->getPort("\\CO"), replacement_output);
+ optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+ module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
@@ -72,21 +88,83 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
}
continue;
}
+
+ if (cell->type == "$__ICE40_CARRY_WRAPPER")
+ {
+ SigSpec non_const_inputs, replacement_output;
+ int count_zeros = 0, count_ones = 0;
+
+ SigBit inbit[3] = {
+ cell->getPort("\\A"),
+ cell->getPort("\\B"),
+ cell->getPort("\\CI")
+ };
+ for (int i = 0; i < 3; i++)
+ if (inbit[i].wire == nullptr) {
+ if (inbit[i] == State::S1)
+ count_ones++;
+ else
+ count_zeros++;
+ } else
+ non_const_inputs.append(inbit[i]);
+
+ if (count_zeros >= 2)
+ replacement_output = State::S0;
+ else if (count_ones >= 2)
+ replacement_output = State::S1;
+ else if (GetSize(non_const_inputs) == 1)
+ replacement_output = non_const_inputs;
+
+ if (GetSize(replacement_output)) {
+ optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+ auto it = cell->attributes.find(ID(SB_LUT4.name));
+ if (it != cell->attributes.end()) {
+ module->rename(cell, it->second.decode_string());
+ decltype(Cell::attributes) new_attr;
+ for (const auto &a : cell->attributes)
+ if (a.first.begins_with("\\SB_LUT4.\\"))
+ new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
+ else if (a.first == ID(src))
+ new_attr.insert(std::make_pair(a.first, a.second));
+ else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
+ continue;
+ else if (a.first.begins_with("\\SB_CARRY.\\"))
+ continue;
+ else
+ log_abort();
+ cell->attributes = std::move(new_attr);
+ }
+ module->connect(cell->getPort("\\CO")[0], replacement_output);
+ module->design->scratchpad_set_bool("opt.did_something", true);
+ log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+ log_id(module), log_id(cell), log_signal(replacement_output));
+ cell->type = "$lut";
+ auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
+ cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
+ cell->setPort("\\Y", cell->getPort("\\O"));
+ cell->unsetPort("\\B");
+ cell->unsetPort("\\CI");
+ cell->unsetPort("\\I0");
+ cell->unsetPort("\\I3");
+ cell->unsetPort("\\CO");
+ cell->unsetPort("\\O");
+ cell->setParam("\\WIDTH", 4);
+ cell->unsetParam("\\I3_IS_CI");
+ }
+ continue;
+ }
}
for (auto cell : sb_lut_cells)
{
SigSpec inbits;
- inbits.append(cell->getPort("\\I0"));
- inbits.append(cell->getPort("\\I1"));
- inbits.append(cell->getPort("\\I2"));
- inbits.append(cell->getPort("\\I3"));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
sigmap.apply(inbits);
- if (unlut_mode)
- goto remap_lut;
-
if (optimized_co.count(inbits[0])) goto remap_lut;
if (optimized_co.count(inbits[1])) goto remap_lut;
if (optimized_co.count(inbits[2])) goto remap_lut;
@@ -104,8 +182,13 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
- cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")}));
- cell->setPort("\\Y", cell->getPort("\\O"));
+ cell->setPort("\\A", SigSpec({
+ get_bit_or_zero(cell->getPort("\\I3")),
+ get_bit_or_zero(cell->getPort("\\I2")),
+ get_bit_or_zero(cell->getPort("\\I1")),
+ get_bit_or_zero(cell->getPort("\\I0"))
+ }));
+ cell->setPort("\\Y", cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");
@@ -120,7 +203,7 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
struct Ice40OptPass : public Pass {
Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -136,14 +219,10 @@ struct Ice40OptPass : public Pass {
log(" opt_clean\n");
log(" while <changed design>\n");
log("\n");
- log("When called with the option -unlut, this command will transform all already\n");
- log("mapped SB_LUT4 cells back to logic.\n");
- log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string opt_expr_args = "-mux_undef -undriven";
- bool unlut_mode = false;
log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
log_push();
@@ -154,10 +233,6 @@ struct Ice40OptPass : public Pass {
opt_expr_args += " -full";
continue;
}
- if (args[argidx] == "-unlut") {
- unlut_mode = true;
- continue;
- }
break;
}
extra_args(args, argidx, design);
@@ -168,7 +243,7 @@ struct Ice40OptPass : public Pass {
log_header(design, "Running ICE40 specific optimizations.\n");
for (auto module : design->selected_modules())
- run_ice40_opts(module, unlut_mode);
+ run_ice40_opts(module);
Pass::call(design, "opt_expr " + opt_expr_args);
Pass::call(design, "opt_merge");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index a49372c8a..d92e40726 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,7 +29,7 @@ struct SynthIce40Pass : public ScriptPass
{
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
- virtual void help() YS_OVERRIDE
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
log("This command runs synthesis for iCE40 FPGAs.\n");
log("\n");
+ log(" -device < hx | lp | u >\n");
+ log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
+ log(" default: hx\n");
+ log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
@@ -45,7 +49,11 @@ struct SynthIce40Pass : public ScriptPass
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -edif <file>\n");
- log(" write the design to the specified edif file. writing of an output file\n");
+ log(" write the design to the specified EDIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
@@ -57,39 +65,68 @@ struct SynthIce40Pass : public ScriptPass
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
- log(" run 'abc' with -dff option\n");
+ log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nocarry\n");
log(" do not use SB_CARRY cells in output netlist\n");
log("\n");
+ log(" -nodffe\n");
+ log(" do not use SB_DFFE* cells in output netlist\n");
+ log("\n");
+ log(" -dffe_min_ce_use <min_ce_use>\n");
+ log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
+ log(" than min_ce_use SB_DFFE* in output netlist\n");
+ log("\n");
log(" -nobram\n");
log(" do not use SB_RAM40_4K* cells in output netlist\n");
log("\n");
+ log(" -dsp\n");
+ log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
+ log("\n");
+ log(" -noabc\n");
+ log(" use built-in Yosys LUT techmapping instead of abc\n");
+ log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
+ log(" -vpr\n");
+ log(" generate an output netlist (and BLIF file) suitable for VPR\n");
+ log(" (this feature is experimental and incomplete)\n");
+ log("\n");
+ log(" -abc9\n");
+ log(" use new ABC9 flow (EXPERIMENTAL)\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
- string top_opt, blif_file, edif_file;
- bool nocarry, nobram, flatten, retime, abc2;
+ string top_opt, blif_file, edif_file, json_file, device_opt;
+ bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9;
+ int min_ce_use;
- virtual void clear_flags() YS_OVERRIDE
+ void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
blif_file = "";
edif_file = "";
+ json_file = "";
nocarry = false;
+ nodffe = false;
+ min_ce_use = -1;
nobram = false;
+ dsp = false;
flatten = true;
retime = false;
+ noabc = false;
abc2 = false;
+ vpr = false;
+ abc9 = false;
+ device_opt = "hx";
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@@ -109,6 +146,10 @@ struct SynthIce40Pass : public ScriptPass
edif_file = args[++argidx];
continue;
}
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
@@ -129,24 +170,61 @@ struct SynthIce40Pass : public ScriptPass
retime = true;
continue;
}
+ if (args[argidx] == "-relut") {
+ // removed, opt_lut is always run
+ continue;
+ }
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
}
+ if (args[argidx] == "-nodffe") {
+ nodffe = true;
+ continue;
+ }
+ if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
+ min_ce_use = atoi(args[++argidx].c_str());
+ continue;
+ }
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
+ if (args[argidx] == "-dsp") {
+ dsp = true;
+ continue;
+ }
+ if (args[argidx] == "-noabc") {
+ noabc = true;
+ continue;
+ }
if (args[argidx] == "-abc2") {
abc2 = true;
continue;
}
+ if (args[argidx] == "-vpr") {
+ vpr = true;
+ continue;
+ }
+ if (args[argidx] == "-abc9") {
+ abc9 = true;
+ continue;
+ }
+ if (args[argidx] == "-device" && argidx+1 < args.size()) {
+ device_opt = args[++argidx];
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
+ log_cmd_error("This command only operates on fully selected designs!\n");
+ if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
+ log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
+
+ if (abc9 && retime)
+ log_cmd_error("-retime option not currently compatible with -abc9!\n");
log_header(design, "Executing SYNTH_ICE40 pass.\n");
log_push();
@@ -156,52 +234,103 @@ struct SynthIce40Pass : public ScriptPass
log_pop();
}
- virtual void script() YS_OVERRIDE
+ void script() YS_OVERRIDE
{
if (check_label("begin"))
{
- run("read_verilog -lib +/ice40/cells_sim.v");
+ std::string define;
+ if (device_opt == "lp")
+ define = "-D ICE40_LP";
+ else if (device_opt == "u")
+ define = "-D ICE40_U";
+ else
+ define = "-D ICE40_HX";
+ run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ run("proc");
}
- if (flatten && check_label("flatten", "(unless -noflatten)"))
+ if (check_label("flatten", "(unless -noflatten)"))
{
- run("proc");
- run("flatten");
- run("tribuf -logic");
- run("deminout");
+ if (flatten) {
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
}
if (check_label("coarse"))
{
- run("synth -run coarse");
+ run("opt_expr");
+ run("opt_clean");
+ run("check");
+ run("opt");
+ run("wreduce");
+ run("peepopt");
+ run("opt_clean");
+ run("share");
+ run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+ run("opt_expr");
+ run("opt_clean");
+ if (help_mode || dsp) {
+ run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first
+ run("wreduce t:$mul");
+ run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+ "-D DSP_NAME=$__MUL16X16", "(if -dsp)");
+ run("select a:mul2dsp", " (if -dsp)");
+ run("setattr -unset mul2dsp", " (if -dsp)");
+ run("opt_expr -fine", " (if -dsp)");
+ run("wreduce", " (if -dsp)");
+ run("select -clear", " (if -dsp)");
+ run("ice40_dsp", " (if -dsp)");
+ run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
+ }
+ run("alumacc");
+ run("opt");
+ run("fsm");
+ run("opt -fast");
+ run("memory -nomap");
+ run("opt_clean");
}
- if (!nobram && check_label("bram", "(skip if -nobram)"))
+ if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/ice40/brams.txt");
run("techmap -map +/ice40/brams_map.v");
+ run("ice40_braminit");
}
- if (check_label("fine"))
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
if (nocarry)
run("techmap");
- else
+ else {
+ run("ice40_wrapcarry");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+ }
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
run("ice40_opt");
}
if (check_label("map_ffs"))
{
run("dffsr2dff");
- run("dff2dffe -direct-match $_DFF_*");
- run("techmap -map +/ice40/cells_map.v");
+ if (!nodffe)
+ run("dff2dffe -direct-match $_DFF_*");
+ if (min_ce_use >= 0) {
+ run("opt_merge");
+ run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+ }
+ run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("ice40_ffinit");
@@ -216,18 +345,44 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_opt", "(only if -abc2)");
}
run("techmap -map +/ice40/latches_map.v");
- run("abc -lut 4");
+ if (noabc || help_mode) {
+ run("simplemap", " (only if -noabc)");
+ run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+ }
+ if (!noabc) {
+ if (abc9) {
+ run("read_verilog -icells -lib +/ice40/abc9_model.v");
+ int wire_delay;
+ if (device_opt == "lp")
+ wire_delay = 400;
+ else if (device_opt == "u")
+ wire_delay = 750;
+ else
+ wire_delay = 250;
+ run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
+ }
+ else
+ run("abc -dress -lut 4", "(skip if -noabc)");
+ }
+ run("ice40_wrapcarry -unwrap");
+ run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("clean");
+ run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
}
if (check_label("map_cells"))
{
- run("techmap -map +/ice40/cells_map.v");
+ if (vpr)
+ run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+ else
+ run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
+
run("clean");
}
if (check_label("check"))
{
+ run("autoname");
run("hierarchy -check");
run("stat");
run("check -noinit");
@@ -235,8 +390,19 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("blif"))
{
- if (!blif_file.empty() || help_mode)
- run(stringf("write_blif -gates -attr -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
+ if (!blif_file.empty() || help_mode) {
+ if (vpr || help_mode) {
+ run(stringf("opt_clean -purge"),
+ " (vpr mode)");
+ run(stringf("write_blif -attr -cname -conn -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()),
+ " (vpr mode)");
+ }
+ if (!vpr)
+ run(stringf("write_blif -gates -attr -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()),
+ " (non-vpr mode)");
+ }
}
if (check_label("edif"))
@@ -244,6 +410,12 @@ struct SynthIce40Pass : public ScriptPass
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
}
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+ }
}
} SynthIce40Pass;
diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index b58f9ad4a..120286550 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -1,2 +1,11 @@
-test_ffs_[01][01][01][01][01]_*
-test_bram_[0-9]*
+/test_ffs_[01][01][01][01][01]_*
+/test_bram_[0-9]*
+/test_dsp_model
+/test_dsp_model.vcd
+/test_dsp_model_ref.v
+/test_dsp_model_uut.v
+/test_dsp_map
+/test_dsp_map.vcd
+/test_dsp_map_tb.v
+/test_dsp_map_top.v
+/test_dsp_map_syn.v
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 160c767fb..ddb80b700 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,6 +1,5 @@
read_verilog test_arith.v
synth_ice40
-techmap -map ../cells_sim.v
rename test gate
read_verilog test_arith.v
@@ -8,3 +7,11 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
+
+synth_ice40 -top gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter
diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh
new file mode 100644
index 000000000..3f7f134e4
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_map.sh
@@ -0,0 +1,107 @@
+#!/bin/bash
+set -ex
+
+for iter in {1..100}
+do
+ SZA=$(( 3 + $RANDOM % 13 ))
+ SZB=$(( 3 + $RANDOM % 13 ))
+ SZO=$(( 3 + $RANDOM % 29 ))
+
+ C0=clk$(( $RANDOM & 1))
+ C1=clk$(( $RANDOM & 1))
+ C2=clk$(( $RANDOM & 1))
+ C3=clk$(( $RANDOM & 1))
+
+ E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+ E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+ E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+ E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+
+ SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
+
+ RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
+ RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
+
+ cat > test_dsp_map_top.v << EOT
+module top (
+ input clk0, clk1, reset,
+ input [$SZA:0] A,
+ input [$SZB:0] B,
+ output [$SZO:0] O
+);
+ reg [15:0] AA, BB;
+ reg [31:0] P, S;
+
+ always @($E0 $C0) AA <= A;
+ always @($E1 $C1) BB <= B;
+ always @($E2 $C2) P <= AA * BB;
+ always @($E3 $C3) S <= $RC ? $RV : S + P;
+ assign O = $SP;
+endmodule
+EOT
+
+ cat > test_dsp_map_tb.v << EOT
+\`timescale 1ns / 1ps
+module testbench;
+ reg clk1, clk0, reset;
+ reg [$SZA:0] A;
+ reg [$SZB:0] B;
+
+ wire [$SZO:0] O_top, O_syn;
+
+ top top_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_top));
+ syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
+
+ initial begin
+ // \$dumpfile("test_dsp_map.vcd");
+ // \$dumpvars(0, testbench);
+
+ #2;
+ clk0 = 0;
+ clk1 = 0;
+ reset = 1;
+ reset = $RC;
+ A = 0;
+ B = 0;
+
+ repeat (3) begin
+ #2; clk0 = ~clk0;
+ #2; clk0 = ~clk0;
+ #2; clk1 = ~clk1;
+ #2; clk1 = ~clk1;
+ end
+
+ repeat (100) begin
+ #2;
+ A = \$urandom;
+ B = \$urandom;
+ reset = \$urandom & \$urandom & \$urandom & \$urandom;
+ if (\$urandom & 1) begin
+ #2; clk0 = ~clk0;
+ #2; clk0 = ~clk0;
+ end else begin
+ #2; clk1 = ~clk1;
+ #2; clk1 = ~clk1;
+ end
+ #2;
+ if (O_top !== O_syn) begin
+ \$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
+ \$stop;
+ end
+ // \$display("OK O_top=O_syn=%b", O_top);
+ end
+
+ \$display("Test passed.");
+ \$finish;
+ end
+endmodule
+EOT
+
+ ../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
+ iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
+ vvp -N test_dsp_map
+done
+
+: ""
+: "#### All tests passed. ####"
+: ""
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
new file mode 100644
index 000000000..1e564d1b2
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+set -ex
+sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+ cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+fi
+for tb in testbench \
+ testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
+ testbench_seq_16x16_A testbench_seq_16x16_B \
+ testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
+ testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
+ testbench_comb_16x16_signedA testbench_comb_16x16_signedB testbench_comb_16x16_signedAB
+do
+ iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
+ vvp -N ./test_dsp_model
+done
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
new file mode 100644
index 000000000..f4f6858f0
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -0,0 +1,567 @@
+`timescale 1ns / 1ps
+
+module testbench;
+ parameter [0:0] NEG_TRIGGER = 0;
+ parameter [0:0] C_REG = 0;
+ parameter [0:0] A_REG = 0;
+ parameter [0:0] B_REG = 0;
+ parameter [0:0] D_REG = 0;
+ parameter [0:0] TOP_8x8_MULT_REG = 0;
+ parameter [0:0] BOT_8x8_MULT_REG = 0;
+ parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
+ parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
+ parameter [1:0] TOPOUTPUT_SELECT = 0;
+ parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
+ parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
+ parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
+ parameter [1:0] BOTOUTPUT_SELECT = 0;
+ parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
+ parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
+ parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
+ parameter [0:0] MODE_8x8 = 0;
+ parameter [0:0] A_SIGNED = 0;
+ parameter [0:0] B_SIGNED = 0;
+
+ reg CLK, CE;
+ reg [15:0] C, A, B, D;
+ reg AHOLD, BHOLD, CHOLD, DHOLD;
+ reg IRSTTOP, IRSTBOT;
+ reg ORSTTOP, ORSTBOT;
+ reg OLOADTOP, OLOADBOT;
+ reg ADDSUBTOP, ADDSUBBOT;
+ reg OHOLDTOP, OHOLDBOT;
+ reg CI, ACCUMCI, SIGNEXTIN;
+
+ output [31:0] REF_O, UUT_O;
+ output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT;
+ output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;
+
+ integer errcount = 0;
+
+ task clkcycle;
+ begin
+ #5;
+ CLK = ~CLK;
+ #10;
+ CLK = ~CLK;
+ #2;
+ if (REF_O !== UUT_O) begin
+ $display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O);
+ errcount = errcount + 1;
+ end
+ if (REF_CO !== UUT_CO) begin
+ $display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO);
+ errcount = errcount + 1;
+ end
+ if (REF_ACCUMCO !== UUT_ACCUMCO) begin
+ $display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO);
+ errcount = errcount + 1;
+ end
+ if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin
+ $display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT);
+ errcount = errcount + 1;
+ end
+ #3;
+ end
+ endtask
+
+ initial begin
+ $dumpfile("test_dsp_model.vcd");
+ $dumpvars(0, testbench);
+
+ #2;
+ CLK = NEG_TRIGGER;
+ CE = 1;
+ {C, A, B, D} = 0;
+ {AHOLD, BHOLD, CHOLD, DHOLD} = 0;
+ {OLOADTOP, OLOADBOT} = 0;
+ {ADDSUBTOP, ADDSUBBOT} = 0;
+ {OHOLDTOP, OHOLDBOT} = 0;
+ {CI, ACCUMCI, SIGNEXTIN} = 0;
+
+ {IRSTTOP, IRSTBOT} = ~0;
+ {ORSTTOP, ORSTBOT} = ~0;
+
+ #3;
+ {IRSTTOP, IRSTBOT} = 0;
+ {ORSTTOP, ORSTBOT} = 0;
+
+ repeat (300) begin
+ clkcycle;
+
+ A = $urandom;
+ B = $urandom;
+ C = $urandom;
+ D = $urandom;
+
+ {AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom;
+ {OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom;
+ {ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom;
+ {OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom;
+ {CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom;
+
+ {IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom;
+ {ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom;
+ end
+
+ if (errcount == 0) begin
+ $display("All tests passed.");
+ $finish;
+ end else begin
+ $display("Caught %1d errors.", errcount);
+ $stop;
+ end
+ end
+
+ SB_MAC16 #(
+ .NEG_TRIGGER (NEG_TRIGGER ),
+ .C_REG (C_REG ),
+ .A_REG (A_REG ),
+ .B_REG (B_REG ),
+ .D_REG (D_REG ),
+ .TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
+ .BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
+ .PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
+ .PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
+ .TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
+ .TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
+ .TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
+ .TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
+ .BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
+ .BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
+ .BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
+ .BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
+ .MODE_8x8 (MODE_8x8 ),
+ .A_SIGNED (A_SIGNED ),
+ .B_SIGNED (B_SIGNED )
+ ) ref (
+ .CLK (CLK ),
+ .CE (CE ),
+ .C (C ),
+ .A (A ),
+ .B (B ),
+ .D (D ),
+ .AHOLD (AHOLD ),
+ .BHOLD (BHOLD ),
+ .CHOLD (CHOLD ),
+ .DHOLD (DHOLD ),
+ .IRSTTOP (IRSTTOP ),
+ .IRSTBOT (IRSTBOT ),
+ .ORSTTOP (ORSTTOP ),
+ .ORSTBOT (ORSTBOT ),
+ .OLOADTOP (OLOADTOP ),
+ .OLOADBOT (OLOADBOT ),
+ .ADDSUBTOP (ADDSUBTOP ),
+ .ADDSUBBOT (ADDSUBBOT ),
+ .OHOLDTOP (OHOLDTOP ),
+ .OHOLDBOT (OHOLDBOT ),
+ .CI (CI ),
+ .ACCUMCI (ACCUMCI ),
+ .SIGNEXTIN (SIGNEXTIN ),
+ .O (REF_O ),
+ .CO (REF_CO ),
+ .ACCUMCO (REF_ACCUMCO ),
+ .SIGNEXTOUT (REF_SIGNEXTOUT)
+ );
+
+ SB_MAC16_UUT #(
+ .NEG_TRIGGER (NEG_TRIGGER ),
+ .C_REG (C_REG ),
+ .A_REG (A_REG ),
+ .B_REG (B_REG ),
+ .D_REG (D_REG ),
+ .TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
+ .BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
+ .PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
+ .PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
+ .TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
+ .TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
+ .TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
+ .TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
+ .BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
+ .BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
+ .BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
+ .BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
+ .MODE_8x8 (MODE_8x8 ),
+ .A_SIGNED (A_SIGNED ),
+ .B_SIGNED (B_SIGNED )
+ ) uut (
+ .CLK (CLK ),
+ .CE (CE ),
+ .C (C ),
+ .A (A ),
+ .B (B ),
+ .D (D ),
+ .AHOLD (AHOLD ),
+ .BHOLD (BHOLD ),
+ .CHOLD (CHOLD ),
+ .DHOLD (DHOLD ),
+ .IRSTTOP (IRSTTOP ),
+ .IRSTBOT (IRSTBOT ),
+ .ORSTTOP (ORSTTOP ),
+ .ORSTBOT (ORSTBOT ),
+ .OLOADTOP (OLOADTOP ),
+ .OLOADBOT (OLOADBOT ),
+ .ADDSUBTOP (ADDSUBTOP ),
+ .ADDSUBBOT (ADDSUBBOT ),
+ .OHOLDTOP (OHOLDTOP ),
+ .OHOLDBOT (OHOLDBOT ),
+ .CI (CI ),
+ .ACCUMCI (ACCUMCI ),
+ .SIGNEXTIN (SIGNEXTIN ),
+ .O (UUT_O ),
+ .CO (UUT_CO ),
+ .ACCUMCO (UUT_ACCUMCO ),
+ .SIGNEXTOUT (UUT_SIGNEXTOUT)
+ );
+endmodule
+
+module testbench_comb_8x8_A;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedA;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (1),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedB;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (1)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedAB;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (1),
+ .B_SIGNED (1)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_B;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedA;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (1),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedB;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (1)
+ ) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedAB;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (1),
+ .B_SIGNED (1)
+ ) testbench ();
+endmodule
+
+module testbench_comb_16x16;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedA;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (1),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedB;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (1)
+ ) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedAB;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (0),
+ .A_REG (0),
+ .B_REG (0),
+ .D_REG (0),
+ .TOP_8x8_MULT_REG (0),
+ .BOT_8x8_MULT_REG (0),
+ .PIPELINE_16x16_MULT_REG1 (0),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (1),
+ .B_SIGNED (1)
+ ) testbench ();
+endmodule
+
+module testbench_seq_16x16_A;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (1),
+ .A_REG (1),
+ .B_REG (1),
+ .D_REG (1),
+ .TOP_8x8_MULT_REG (1),
+ .BOT_8x8_MULT_REG (1),
+ .PIPELINE_16x16_MULT_REG1 (1),
+ .PIPELINE_16x16_MULT_REG2 (1),
+ .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
+
+module testbench_seq_16x16_B;
+ testbench #(
+ .NEG_TRIGGER (0),
+ .C_REG (1),
+ .A_REG (1),
+ .B_REG (1),
+ .D_REG (1),
+ .TOP_8x8_MULT_REG (1),
+ .BOT_8x8_MULT_REG (1),
+ .PIPELINE_16x16_MULT_REG1 (1),
+ .PIPELINE_16x16_MULT_REG2 (0),
+ .TOPOUTPUT_SELECT (1), // 0=P, 1=Q, 2=8x8, 3=16x16
+ .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+ .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
+ .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .BOTOUTPUT_SELECT (1), // 0=R, 1=S, 2=8x8, 3=16x16
+ .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+ .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
+ .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
+ .MODE_8x8 (0),
+ .A_SIGNED (0),
+ .B_SIGNED (0)
+ ) testbench ();
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-14 09:20:21 +0000