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-rw-r--r--techlibs/ice40/Makefile.inc1
-rw-r--r--techlibs/ice40/cells_sim.v21
-rw-r--r--techlibs/ice40/ice40_ffssr.cc3
-rw-r--r--techlibs/ice40/ice40_opt.cc15
-rw-r--r--techlibs/ice40/ice40_unlut.cc106
-rw-r--r--techlibs/ice40/synth_ice40.cc48
6 files changed, 179 insertions, 15 deletions
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 14761c6c8..2750901c8 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/ice40/synth_ice40.o
OBJS += techlibs/ice40/ice40_ffssr.o
OBJS += techlibs/ice40/ice40_ffinit.o
OBJS += techlibs/ice40/ice40_opt.o
+OBJS += techlibs/ice40/ice40_unlut.o
GENFILES += techlibs/ice40/brams_init1.vh
GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e0a07af32..38ed45981 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -409,6 +409,7 @@ module SB_RAM40_4K (
initial begin
for (i=0; i<16; i=i+1) begin
+`ifdef YOSYS
memory[ 0*16 + i] <= INIT_0[16*i +: 16];
memory[ 1*16 + i] <= INIT_1[16*i +: 16];
memory[ 2*16 + i] <= INIT_2[16*i +: 16];
@@ -425,6 +426,24 @@ module SB_RAM40_4K (
memory[13*16 + i] <= INIT_D[16*i +: 16];
memory[14*16 + i] <= INIT_E[16*i +: 16];
memory[15*16 + i] <= INIT_F[16*i +: 16];
+`else
+ memory[ 0*16 + i] = INIT_0[16*i +: 16];
+ memory[ 1*16 + i] = INIT_1[16*i +: 16];
+ memory[ 2*16 + i] = INIT_2[16*i +: 16];
+ memory[ 3*16 + i] = INIT_3[16*i +: 16];
+ memory[ 4*16 + i] = INIT_4[16*i +: 16];
+ memory[ 5*16 + i] = INIT_5[16*i +: 16];
+ memory[ 6*16 + i] = INIT_6[16*i +: 16];
+ memory[ 7*16 + i] = INIT_7[16*i +: 16];
+ memory[ 8*16 + i] = INIT_8[16*i +: 16];
+ memory[ 9*16 + i] = INIT_9[16*i +: 16];
+ memory[10*16 + i] = INIT_A[16*i +: 16];
+ memory[11*16 + i] = INIT_B[16*i +: 16];
+ memory[12*16 + i] = INIT_C[16*i +: 16];
+ memory[13*16 + i] = INIT_D[16*i +: 16];
+ memory[14*16 + i] = INIT_E[16*i +: 16];
+ memory[15*16 + i] = INIT_F[16*i +: 16];
+`endif
end
end
@@ -928,6 +947,7 @@ module SB_SPRAM256KA (
output reg [15:0] DATAOUT
);
`ifndef BLACKBOX
+`ifndef EQUIV
reg [15:0] mem [0:16383];
wire off = SLEEP || !POWEROFF;
integer i;
@@ -954,6 +974,7 @@ module SB_SPRAM256KA (
end
end
`endif
+`endif
endmodule
(* blackbox *)
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 668df09dd..a7649d7a0 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -81,6 +81,9 @@ struct Ice40FfssrPass : public Pass {
for (auto cell : ff_cells)
{
+ if (cell->get_bool_attribute("\\dont_touch"))
+ continue;
+
SigSpec sig_d = cell->getPort("\\D");
if (GetSize(sig_d) < 1)
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 162740059..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -33,7 +33,7 @@ static SigBit get_bit_or_zero(const SigSpec &sig)
return sig[0];
}
-static void run_ice40_opts(Module *module, bool unlut_mode)
+static void run_ice40_opts(Module *module)
{
pool<SigBit> optimized_co;
vector<Cell*> sb_lut_cells;
@@ -95,9 +95,6 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
sigmap.apply(inbits);
- if (unlut_mode)
- goto remap_lut;
-
if (optimized_co.count(inbits[0])) goto remap_lut;
if (optimized_co.count(inbits[1])) goto remap_lut;
if (optimized_co.count(inbits[2])) goto remap_lut;
@@ -152,14 +149,10 @@ struct Ice40OptPass : public Pass {
log(" opt_clean\n");
log(" while <changed design>\n");
log("\n");
- log("When called with the option -unlut, this command will transform all already\n");
- log("mapped SB_LUT4 cells back to logic.\n");
- log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string opt_expr_args = "-mux_undef -undriven";
- bool unlut_mode = false;
log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
log_push();
@@ -170,10 +163,6 @@ struct Ice40OptPass : public Pass {
opt_expr_args += " -full";
continue;
}
- if (args[argidx] == "-unlut") {
- unlut_mode = true;
- continue;
- }
break;
}
extra_args(args, argidx, design);
@@ -184,7 +173,7 @@ struct Ice40OptPass : public Pass {
log_header(design, "Running ICE40 specific optimizations.\n");
for (auto module : design->selected_modules())
- run_ice40_opts(module, unlut_mode);
+ run_ice40_opts(module);
Pass::call(design, "opt_expr " + opt_expr_args);
Pass::call(design, "opt_merge");
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
new file mode 100644
index 000000000..2428a8e78
--- /dev/null
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -0,0 +1,106 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+ if (GetSize(sig) == 0)
+ return State::S0;
+ return sig[0];
+}
+
+static void run_ice40_unlut(Module *module)
+{
+ SigMap sigmap(module);
+
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\SB_LUT4")
+ {
+ SigSpec inbits;
+
+ inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
+ inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
+ sigmap.apply(inbits);
+
+ log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
+
+ cell->type ="$lut";
+ cell->setParam("\\WIDTH", 4);
+ cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
+ cell->unsetParam("\\LUT_INIT");
+
+ cell->setPort("\\A", SigSpec({
+ get_bit_or_zero(cell->getPort("\\I3")),
+ get_bit_or_zero(cell->getPort("\\I2")),
+ get_bit_or_zero(cell->getPort("\\I1")),
+ get_bit_or_zero(cell->getPort("\\I0"))
+ }));
+ cell->setPort("\\Y", cell->getPort("\\O")[0]);
+ cell->unsetPort("\\I0");
+ cell->unsetPort("\\I1");
+ cell->unsetPort("\\I2");
+ cell->unsetPort("\\I3");
+ cell->unsetPort("\\O");
+
+ cell->check();
+ }
+ }
+}
+
+struct Ice40UnlutPass : public Pass {
+ Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" ice40_unlut [options] [selection]\n");
+ log("\n");
+ log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
+ log_push();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ // if (args[argidx] == "-???") {
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ run_ice40_unlut(module);
+ }
+} Ice40UnlutPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b0687e5e3..37b924dfd 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -63,15 +63,25 @@ struct SynthIce40Pass : public ScriptPass
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
+ log(" -relut\n");
+ log(" combine LUTs after synthesis\n");
+ log("\n");
log(" -nocarry\n");
log(" do not use SB_CARRY cells in output netlist\n");
log("\n");
log(" -nodffe\n");
log(" do not use SB_DFFE* cells in output netlist\n");
log("\n");
+ log(" -dffe_min_ce_use <min_ce_use>\n");
+ log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
+ log(" than min_ce_use SB_DFFE*in output netlist\n");
+ log("\n");
log(" -nobram\n");
log(" do not use SB_RAM40_4K* cells in output netlist\n");
log("\n");
+ log(" -noabc\n");
+ log(" use built-in Yosys LUT techmapping instead of abc\n");
+ log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
@@ -86,7 +96,8 @@ struct SynthIce40Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
+ bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
+ int min_ce_use;
void clear_flags() YS_OVERRIDE
{
@@ -96,9 +107,12 @@ struct SynthIce40Pass : public ScriptPass
json_file = "";
nocarry = false;
nodffe = false;
+ min_ce_use = -1;
nobram = false;
flatten = true;
retime = false;
+ relut = false;
+ noabc = false;
abc2 = false;
vpr = false;
}
@@ -147,6 +161,10 @@ struct SynthIce40Pass : public ScriptPass
retime = true;
continue;
}
+ if (args[argidx] == "-relut") {
+ relut = true;
+ continue;
+ }
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
@@ -155,10 +173,18 @@ struct SynthIce40Pass : public ScriptPass
nodffe = true;
continue;
}
+ if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
+ min_ce_use = std::stoi(args[++argidx]);
+ continue;
+ }
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
+ if (args[argidx] == "-noabc") {
+ noabc = true;
+ continue;
+ }
if (args[argidx] == "-abc2") {
abc2 = true;
continue;
@@ -214,6 +240,10 @@ struct SynthIce40Pass : public ScriptPass
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
if (nocarry)
run("techmap");
else
@@ -228,6 +258,10 @@ struct SynthIce40Pass : public ScriptPass
run("dffsr2dff");
if (!nodffe)
run("dff2dffe -direct-match $_DFF_*");
+ if (min_ce_use >= 0) {
+ run("opt_merge");
+ run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+ }
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
@@ -243,8 +277,18 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_opt", "(only if -abc2)");
}
run("techmap -map +/ice40/latches_map.v");
- run("abc -lut 4");
+ if (noabc || help_mode) {
+ run("simplemap", " (only if -noabc)");
+ run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+ }
+ if (!noabc) {
+ run("abc -lut 4", "(skip if -noabc)");
+ }
run("clean");
+ if (relut || help_mode) {
+ run("ice40_unlut", " (only if -relut)");
+ run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
+ }
}
if (check_label("map_cells"))
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 05:57:32 +0000