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-rw-r--r--techlibs/ice40/abc_hx.box112
-rw-r--r--techlibs/ice40/abc_lp.box110
-rw-r--r--techlibs/ice40/abc_u.box112
-rw-r--r--techlibs/ice40/cells_sim.v11
-rw-r--r--techlibs/ice40/ice40_unlut.cc2
-rw-r--r--techlibs/ice40/synth_ice40.cc17
6 files changed, 39 insertions, 325 deletions
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index a0655643d..f8e12b527 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -1,113 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
# NB: Inputs/Outputs must be ordered alphabetically
+# (with exceptions for carry in/out)
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
-
-# Inputs: CI I0 I1
+# Inputs: I0 I1 CI
# Outputs: CO
-SB_CARRY 21 1 3 1
-126 259 231
+# (NB: carry chain input/output must be last
+# input/output and have been moved there
+# overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+259 231 126
# Inputs: I0 I1 I2 I3
# Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index eb1cd0937..fbe4c56e6 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -1,113 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
+# (with exceptions for carry in/out)
# Inputs: CI I0 I1
# Outputs: CO
-SB_CARRY 21 1 3 1
-186 675 609
+# (NB: carry chain input/output must be last
+# input/output and have been moved there
+# overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+675 609 186
# Inputs: I0 I1 I2 I3
# Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 3b5834e40..f44deabc4 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -1,113 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
# NB: Inputs/Outputs must be ordered alphabetically
+# (with exceptions for carry in/out)
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
-
-# Inputs: CI I0 I1
+# Inputs: I0 I1 CI
# Outputs: CO
-SB_CARRY 21 1 3 1
-278 675 609
+# (NB: carry chain input/output must be last
+# input/output and have been moved there
+# overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+675 609 278
# Inputs: I0 I1 I2 I3
# Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
1285 1231 1205 874
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 031afa85c..b746ba4e5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
// SiliconBlue Logic Cells
-(* abc_box_id = 22, lib_whitebox *)
+(* abc_box_id = 2, lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,20 +136,16 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
-(* abc_box_id = 21, abc_carry, lib_whitebox *)
-module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
// Positive Edge SiliconBlue FF Cells
module SB_DFF (output `SB_DFF_REG, input C, D);
-`ifndef _ABC
always @(posedge C)
Q <= D;
-`else
- always @* Q <= D;
-`endif
endmodule
module SB_DFFE (output `SB_DFF_REG, input C, E, D);
@@ -896,7 +892,6 @@ module SB_WARMBOOT (
);
endmodule
-(* nomem2reg *)
module SB_SPRAM256KA (
input [13:0] ADDRESS,
input [15:0] DATAIN,
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index 2428a8e78..d16e6e6a3 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
}
struct Ice40UnlutPass : public Pass {
- Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+ Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d8e9786c5..9dd5d81f7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -38,8 +38,8 @@ struct SynthIce40Pass : public ScriptPass
log("This command runs synthesis for iCE40 FPGAs.\n");
log("\n");
log(" -device < hx | lp | u >\n");
- log(" optimise the synthesis netlist for the specified device.\n");
- log(" HX is the default target if no device argument specified.\n");
+ log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
+ log(" default: hx\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");
@@ -105,7 +105,6 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
}
-
string top_opt, blif_file, edif_file, json_file, abc, device_opt;
bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
int min_ce_use;
@@ -331,8 +330,16 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
}
if (!noabc) {
- if (abc == "abc9")
- run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+ if (abc == "abc9") {
+ int wire_delay;
+ if (device_opt == "lp")
+ wire_delay = 400;
+ else if (device_opt == "u")
+ wire_delay = 750;
+ else
+ wire_delay = 250;
+ run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+ }
else
run(abc + " -dress -lut 4", "(skip if -noabc)");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-29 19:23:32 +0000