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-rw-r--r--techlibs/ice40/abc_hx.box8
-rw-r--r--techlibs/ice40/abc_lp.box8
-rw-r--r--techlibs/ice40/abc_u.box8
-rw-r--r--techlibs/ice40/cells_sim.v211
-rw-r--r--techlibs/ice40/ice40_opt.cc9
-rw-r--r--techlibs/ice40/synth_ice40.cc9
6 files changed, 203 insertions, 50 deletions
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c0ea742e2..3ea70bc91 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-400 379 316
-259 231 126
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+400 379 449 316 316
+259 231 - - 126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index d73b6d649..473e92fe9 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-589 558 465
-675 609 186
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+589 558 661 465 465
+675 609 - - 186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 42d666051..f00e247b8 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-1231 1205 874
-675 609 278
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+1231 1205 1285 874 874
+675 609 - - 278
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index ab04808f4..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
// SiliconBlue IO Cells
module SB_IO (
@@ -142,13 +146,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
endmodule
(* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
- (* abc_carry *) output CO,
+module \$__ICE40_CARRY_WRAPPER (
+ (* abc_carry *)
+ output CO,
output O,
- input A,
- input B,
- (* abc_carry *) input CI
+ input A, B,
+ (* abc_carry *)
+ input CI,
+ input I0, I3
);
+ parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
@@ -156,34 +163,52 @@ module \$__ICE40_FULL_ADDER (
.CO(CO)
);
SB_LUT4 #(
- // I0: 1010 1010 1010 1010
- // I1: 1100 1100 1100 1100
- // I2: 1111 0000 1111 0000
- // I3: 1111 1111 0000 0000
- .LUT_INIT(16'b 0110_1001_1001_0110)
+ .LUT_INIT(LUT)
) adder (
- .I0(1'b0),
+ .I0(I0),
.I1(A),
.I2(B),
- .I3(CI),
+ .I3(I3),
.O(O)
);
endmodule
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+
// Positive Edge SiliconBlue FF Cells
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, D
+);
always @(posedge C)
Q <= D;
endmodule
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, D
+);
always @(posedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(posedge C)
if (R)
Q <= 0;
@@ -191,7 +216,13 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -199,7 +230,13 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(posedge C)
if (S)
Q <= 1;
@@ -207,7 +244,13 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -215,7 +258,13 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(posedge C)
if (E) begin
if (R)
@@ -225,7 +274,13 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -233,7 +288,13 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(posedge C)
if (E) begin
if (S)
@@ -243,7 +304,13 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -253,18 +320,36 @@ endmodule
// Negative Edge SiliconBlue FF Cells
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, D
+);
always @(negedge C)
Q <= D;
endmodule
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, D
+);
always @(negedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(negedge C)
if (R)
Q <= 0;
@@ -272,7 +357,13 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -280,7 +371,13 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(negedge C)
if (S)
Q <= 1;
@@ -288,7 +385,13 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -296,7 +399,13 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(negedge C)
if (E) begin
if (R)
@@ -306,7 +415,13 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -314,7 +429,13 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(negedge C)
if (E) begin
if (S)
@@ -324,7 +445,13 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -335,6 +462,9 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -503,6 +633,9 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -568,6 +701,9 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -633,6 +769,9 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -701,7 +840,12 @@ endmodule
module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
- output LO, O, COUT
+ output LO,
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output O,
+ output COUT
);
parameter [15:0] LUT_INIT = 0;
@@ -1301,6 +1445,7 @@ module SB_MAC16 (
input ADDSUBTOP, ADDSUBBOT,
input OHOLDTOP, OHOLDBOT,
input CI, ACCUMCI, SIGNEXTIN,
+ //`ABC_ARRIVAL_U(1984) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [31:0] O,
output CO, ACCUMCO, SIGNEXTOUT
);
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
continue;
}
- if (cell->type == "$__ICE40_FULL_ADDER")
+ if (cell->type == "$__ICE40_CARRY_WRAPPER")
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@@ -114,16 +114,17 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
- log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+ log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
- cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+ cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
+ cell->unsetPort("\\I0");
+ cell->unsetPort("\\I3");
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
- cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
cell->setParam("\\WIDTH", 4);
}
continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..a3890268a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -icells -lib +/ice40/cells_sim.v");
+ std::string define;
+ if (device_opt == "lp")
+ define = "-D ICE40_LP";
+ else if (device_opt == "u")
+ define = "-D ICE40_U";
+ else
+ define = "-D ICE40_HX";
+ run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 22:46:10 +0000