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-rw-r--r--techlibs/ice40/Makefile.inc7
-rw-r--r--techlibs/ice40/abc.v12
-rw-r--r--techlibs/ice40/cells_map.v18
-rw-r--r--techlibs/ice40/cells_sim.v51
-rw-r--r--techlibs/ice40/hx.box13
-rw-r--r--techlibs/ice40/hx.lut6
-rw-r--r--techlibs/ice40/lp.box13
-rw-r--r--techlibs/ice40/lp.lut6
-rw-r--r--techlibs/ice40/synth_ice40.cc35
-rw-r--r--techlibs/ice40/u.box13
-rw-r--r--techlibs/ice40/u.lut6
11 files changed, 144 insertions, 36 deletions
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f..cb2121a11 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,13 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
new file mode 100644
index 000000000..e2a54a42c
--- /dev/null
+++ b/techlibs/ice40/abc.v
@@ -0,0 +1,12 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+ assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+ parameter [15:0] LUT_INIT = 0;
+ // Indicate this is a black-box
+ assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..287c48b11 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -37,20 +37,24 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
- SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+ localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+ SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
end else
if (WIDTH == 2) begin
- SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+ localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}};
+ SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0]));
end else
if (WIDTH == 3) begin
- SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+ localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}};
+ SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0]));
end else
if (WIDTH == 4) begin
+ localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+ .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..70cd51ed1 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -132,18 +132,18 @@ endmodule
// Positive Edge SiliconBlue FF Cells
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
always @(posedge C)
Q <= D;
endmodule
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
always @(posedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(posedge C)
if (R)
Q <= 0;
@@ -151,7 +151,7 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -159,7 +159,7 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(posedge C)
if (S)
Q <= 1;
@@ -167,7 +167,7 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -175,7 +175,7 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(posedge C)
if (E) begin
if (R)
@@ -185,7 +185,7 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -193,7 +193,7 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(posedge C)
if (E) begin
if (S)
@@ -203,7 +203,7 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -213,18 +213,18 @@ endmodule
// Negative Edge SiliconBlue FF Cells
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
always @(negedge C)
Q <= D;
endmodule
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
always @(negedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(negedge C)
if (R)
Q <= 0;
@@ -232,7 +232,7 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -240,7 +240,7 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(negedge C)
if (S)
Q <= 1;
@@ -248,7 +248,7 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -256,7 +256,7 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(negedge C)
if (E) begin
if (R)
@@ -266,7 +266,7 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -274,7 +274,7 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(negedge C)
if (E) begin
if (S)
@@ -284,7 +284,7 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -295,7 +295,7 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
@@ -463,7 +463,7 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
@@ -528,7 +528,7 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
@@ -593,7 +593,7 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
@@ -881,12 +881,13 @@ module SB_WARMBOOT (
);
endmodule
+(* nomem2reg *)
module SB_SPRAM256KA (
input [13:0] ADDRESS,
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
- output reg [15:0] DATAOUT
+ (* abc_flop_q *) output reg [15:0] DATAOUT
);
`ifndef BLACKBOX
`ifndef EQUIV
diff --git a/techlibs/ice40/hx.box b/techlibs/ice40/hx.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/hx.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/hx.lut b/techlibs/ice40/hx.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/hx.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+# I3 I2 I1 I0
+1 1 316
+2 1 316 379
+3 1 316 379 400
+4 1 316 379 400 449
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/lp.box
new file mode 100644
index 000000000..7eb8e86e0
--- /dev/null
+++ b/techlibs/ice40/lp.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+186 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+465 558 589 661
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+# I3 I2 I1 I0
+1 1 465
+2 1 465 558
+3 1 465 558 589
+4 1 465 558 589 661
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8899bfcc4..7c95588e4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
log("This command runs synthesis for iCE40 FPGAs.\n");
log("\n");
+ log(" -device < hx | lp | u >\n");
+ log(" optimise the synthesis netlist for the specified device.\n");
+ log(" HX is the default target if no device argument specified.\n");
+ log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
@@ -92,13 +96,17 @@ struct SynthIce40Pass : public ScriptPass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
+ log(" -abc9\n");
+ log(" use abc9 instead of abc\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
- string top_opt, blif_file, edif_file, json_file;
+
+ string top_opt, blif_file, edif_file, json_file, abc, device_opt;
bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
int min_ce_use;
@@ -119,6 +127,8 @@ struct SynthIce40Pass : public ScriptPass
noabc = false;
abc2 = false;
vpr = false;
+ abc = "abc";
+ device_opt = "hx";
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -201,12 +211,22 @@ struct SynthIce40Pass : public ScriptPass
vpr = true;
continue;
}
+ if (args[argidx] == "-abc9") {
+ abc = "abc9";
+ continue;
+ }
+ if (args[argidx] == "-device" && argidx+1 < args.size()) {
+ device_opt = args[++argidx];
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
+ if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
+ log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
log_header(design, "Executing SYNTH_ICE40 pass.\n");
log_push();
@@ -274,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run(abc + " -dff", "(only if -retime)");
run("ice40_opt");
}
@@ -298,7 +318,7 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("map_luts"))
{
if (abc2 || help_mode) {
- run("abc", " (only if -abc2)");
+ run(abc, " (only if -abc2)");
run("ice40_opt", "(only if -abc2)");
}
run("techmap -map +/ice40/latches_map.v");
@@ -307,7 +327,14 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
}
if (!noabc) {
- run("abc -dress -lut 4", "(skip if -noabc)");
+ if (abc == "abc9") {
+ run("read_verilog +/ice40/abc.v");
+ run("techmap -map +/techmap.v A:abc_box_id");
+ run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+ run("blackbox A:abc_box_id");
+ }
+ else
+ run(abc + " -lut 4", "(skip if -noabc)");
}
run("clean");
if (relut || help_mode) {
diff --git a/techlibs/ice40/u.box b/techlibs/ice40/u.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/u.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/u.lut b/techlibs/ice40/u.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/u.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+# I3 I2 I1 I0
+1 1 874
+2 1 874 1205
+3 1 874 1205 1231
+4 1 874 1205 1231 1285
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 05:25:11 +0000