2 files changed, 40 insertions, 12 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2e1c6807a..52e8e2e3a 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -302,7 +302,9 @@ endmodule
 (* abc9_flop, lib_whitebox *)
 module SB_DFFE (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -589,7 +591,10 @@ endmodule
 (* abc9_flop, lib_whitebox *)
 module SB_DFFESR (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input R,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -647,7 +652,10 @@ endmodule
 (* abc9_box, lib_whitebox *)
 module SB_DFFER (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input R,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -724,7 +732,10 @@ endmodule
 (* abc9_flop, lib_whitebox *)
 module SB_DFFESS (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input S,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -782,7 +793,10 @@ endmodule
 (* abc9_box, lib_whitebox *)
 module SB_DFFES (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input S,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -899,7 +913,9 @@ endmodule
 (* abc9_flop, lib_whitebox *)
 module SB_DFFNE (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -1186,7 +1202,10 @@ endmodule
 (* abc9_flop, lib_whitebox *)
 module SB_DFFNESR (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input R,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -1244,7 +1263,10 @@ endmodule
 (* abc9_box, lib_whitebox *)
 module SB_DFFNER (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input R,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -1321,7 +1343,10 @@ endmodule
 (* abc9_flop, lib_whitebox *)
 module SB_DFFNESS (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input S,
+	input D
 );
 	`SB_DFF_INIT
 
@@ -1379,7 +1404,10 @@ endmodule
 (* abc9_box, lib_whitebox *)
 module SB_DFFNES (
 	output reg Q,
-	input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
+	input C,
+	input E `ICE40_DEFAULT_ASSIGNMENT_1,
+	input S,
+	input D
 );
 	`SB_DFF_INIT
 
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 1174f6e04..2ae859efe 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -45,8 +45,8 @@ struct SynthIce40Pass : public ScriptPass
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
 		log("    -device < hx | lp | u >\n");
-		log("        relevant only for '-abc9' flow, optimise timing for the specified device.\n");
-		log("        default: hx\n");
+		log("        relevant only for '-abc9' flow, optimise timing for the specified\n");
+		log("        device. default: hx\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");