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-rw-r--r--techlibs/intel/common/altpll_bb.v8
-rw-r--r--[-rwxr-xr-x]techlibs/intel/common/brams.txt0
-rw-r--r--[-rwxr-xr-x]techlibs/intel/common/brams_map.v58
-rw-r--r--[-rwxr-xr-x]techlibs/intel/common/m9k_bb.v12
4 files changed, 39 insertions, 39 deletions
diff --git a/techlibs/intel/common/altpll_bb.v b/techlibs/intel/common/altpll_bb.v
index 27eef0f86..d2e6a3643 100644
--- a/techlibs/intel/common/altpll_bb.v
+++ b/techlibs/intel/common/altpll_bb.v
@@ -19,7 +19,7 @@
/* No clearbox model */
`ifdef NO_CLEARBOX
(* blackbox *)
-module altpll
+module altpll
( inclk,
fbin,
pllena,
@@ -62,7 +62,7 @@ module altpll
c2,
c3,
c4);
-
+
parameter intended_device_family = "MAX 10";
parameter operation_mode = "NORMAL";
parameter pll_type = "AUTO";
@@ -340,7 +340,7 @@ module altpll
input phasestep;
input configupdate;
inout fbmimicbidir;
-
+
output [width_clock-1:0] clk;
output [3:0] extclk;
@@ -361,6 +361,6 @@ module altpll
output fref;
output icdrclk;
output c0, c1, c2, c3, c4;
-
+
endmodule // altpll
`endif
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt
index 3bf21afc9..3bf21afc9 100755..100644
--- a/techlibs/intel/common/brams.txt
+++ b/techlibs/intel/common/brams.txt
diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v
index d8413159d..fae4af2ab 100755..100644
--- a/techlibs/intel/common/brams_map.v
+++ b/techlibs/intel/common/brams_map.v
@@ -2,11 +2,11 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
parameter CFG_ABITS = 8;
parameter CFG_DBITS = 36;
- parameter ABITS = "1";
- parameter DBITS = "1";
+ parameter ABITS = "1";
+ parameter DBITS = "1";
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
-
+
input CLK2;
input CLK3;
//Read data
@@ -19,7 +19,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
input B1EN;
wire [CFG_DBITS-1:0] B1DATA_t;
-
+
localparam MODE = CFG_DBITS == 1 ? 1:
CFG_DBITS == 2 ? 2:
CFG_DBITS == 4 ? 3:
@@ -30,7 +30,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
CFG_DBITS == 32 ? 8:
CFG_DBITS == 36 ? 9:
'bx;
-
+
localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
CFG_DBITS == 2 ? 4096:
CFG_DBITS == 4 ? 2048:
@@ -41,32 +41,32 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
CFG_DBITS == 32 ? 256:
CFG_DBITS == 36 ? 256:
'bx;
-
- altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
- .clock_enable_input_a ("ALTERNATE" ),
- .clock_enable_output_b ("NORMAL" ),
- .clock_enable_output_a ("NORMAL" ),
- .wrcontrol_aclr_a ("NONE" ),
- .indata_aclr_a ("NONE" ),
- .address_aclr_a ("NONE" ),
- .outdata_aclr_a ("NONE" ),
- .outdata_reg_a ("UNREGISTERED"),
- .operation_mode ("SINGLE_PORT" ),
- .intended_device_family ("CYCLONE IVE" ),
- .outdata_reg_a ("UNREGISTERED"),
- .lpm_type ("altsyncram" ),
- .init_type ("unused" ),
+
+ altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
+ .clock_enable_input_a ("ALTERNATE" ),
+ .clock_enable_output_b ("NORMAL" ),
+ .clock_enable_output_a ("NORMAL" ),
+ .wrcontrol_aclr_a ("NONE" ),
+ .indata_aclr_a ("NONE" ),
+ .address_aclr_a ("NONE" ),
+ .outdata_aclr_a ("NONE" ),
+ .outdata_reg_a ("UNREGISTERED"),
+ .operation_mode ("SINGLE_PORT" ),
+ .intended_device_family ("CYCLONE IVE" ),
+ .outdata_reg_a ("UNREGISTERED"),
+ .lpm_type ("altsyncram" ),
+ .init_type ("unused" ),
.ram_block_type ("AUTO" ),
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
.power_up_uninitialized ("FALSE"),
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
.width_byteena_a (1), // Forced value
- .numwords_b ( NUMWORDS ),
- .numwords_a ( NUMWORDS ),
- .widthad_b ( CFG_ABITS ),
- .width_b ( CFG_DBITS ),
- .widthad_a ( CFG_ABITS ),
- .width_a ( CFG_DBITS )
+ .numwords_b ( NUMWORDS ),
+ .numwords_a ( NUMWORDS ),
+ .widthad_b ( CFG_ABITS ),
+ .width_b ( CFG_DBITS ),
+ .widthad_a ( CFG_ABITS ),
+ .width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ (
.data_a(B1DATA),
.address_a(B1ADDR),
@@ -78,16 +78,16 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.wren_b(1'b0),
.rden_b(1'b0),
.q_b(1'b0),
- .clock0(CLK2),
+ .clock0(CLK2),
.clock1(1'b1), // Unused in single port mode
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
- .aclr0(1'b0),
+ .aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0));
-
+
endmodule
diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v
index 4370a105e..b18a752f5 100755..100644
--- a/techlibs/intel/common/m9k_bb.v
+++ b/techlibs/intel/common/m9k_bb.v
@@ -17,10 +17,10 @@
*
*/
(* blackbox *)
-module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
- q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
+module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
+ q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
-
+
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
@@ -33,7 +33,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_a = "UNREGISTERED";
- parameter lpm_type = "altsyncram";
+ parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
@@ -46,7 +46,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
-
+
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
@@ -66,5 +66,5 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
-
+
endmodule // altsyncram
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 21:15:45 +0000