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Diffstat (limited to 'techlibs/intel/synth_intel.cc')
-rw-r--r--techlibs/intel/synth_intel.cc75
1 files changed, 33 insertions, 42 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 09c9ba3af..e5dc1adc7 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -38,9 +38,9 @@ struct SynthIntelPass : public ScriptPass {
log("\n");
log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
- log(" MAX10 is the default target if not family argument specified.\n");
+ log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
- log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
+ log(" Cyclone V and Arria 10 GX devices are experimental.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
@@ -61,11 +61,11 @@ struct SynthIntelPass : public ScriptPass {
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
- log(" -noiopads\n");
- log(" do not use altsyncram cells in output netlist\n");
+ log(" -iopads\n");
+ log(" use IO pad cells in output netlist\n");
log("\n");
log(" -nobram\n");
- log(" do not use altsyncram cells in output netlist\n");
+ log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
@@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass {
}
string top_opt, family_opt, vout_file, blif_file;
- bool retime, flatten, nobram, noiopads;
+ bool retime, flatten, nobram, iopads;
void clear_flags() YS_OVERRIDE
{
@@ -90,7 +90,7 @@ struct SynthIntelPass : public ScriptPass {
retime = false;
flatten = true;
nobram = false;
- noiopads = false;
+ iopads = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -125,8 +125,8 @@ struct SynthIntelPass : public ScriptPass {
run_to = args[argidx].substr(pos + 1);
continue;
}
- if (args[argidx] == "-noiopads") {
- noiopads = true;
+ if (args[argidx] == "-iopads") {
+ iopads = true;
continue;
}
if (args[argidx] == "-nobram") {
@@ -147,9 +147,13 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
- if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
- family_opt != "cycloneive" && family_opt != "cyclone10")
- log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
+ if (family_opt != "max10" &&
+ family_opt != "a10gx" &&
+ family_opt != "cyclonev" &&
+ family_opt != "cycloneiv" &&
+ family_opt != "cycloneive" &&
+ family_opt != "cyclone10")
+ log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n");
log_push();
@@ -162,18 +166,9 @@ struct SynthIntelPass : public ScriptPass {
void script() YS_OVERRIDE
{
if (check_label("begin")) {
- if (check_label("family") && family_opt == "max10")
- run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
- else if (check_label("family") && family_opt == "a10gx")
- run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
- else if (check_label("family") && family_opt == "cyclonev")
- run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
- else if (check_label("family") && family_opt == "cyclone10")
- run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
- else if (check_label("family") && family_opt == "cycloneiv")
- run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
- else
- run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
+ if (check_label("family"))
+ run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
+
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@@ -191,12 +186,19 @@ struct SynthIntelPass : public ScriptPass {
run("synth -run coarse");
}
- if (!nobram && check_label("bram", "(skip if -nobram)")) {
- run("memory_bram -rules +/intel/common/brams.txt");
- run("techmap -map +/intel/common/brams_map.v");
+ if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
+ if (family_opt == "cycloneiv" ||
+ family_opt == "cycloneive" ||
+ family_opt == "max10" ||
+ help_mode) {
+ run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
+ run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
+ } else {
+ log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str());
+ }
}
- if (check_label("fine")) {
+ if (check_label("map_ffram")) {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
@@ -220,20 +222,9 @@ struct SynthIntelPass : public ScriptPass {
}
if (check_label("map_cells")) {
- if (!noiopads)
- run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
- if (family_opt == "max10")
- run("techmap -map +/intel/max10/cells_map.v");
- else if (family_opt == "a10gx")
- run("techmap -map +/intel/a10gx/cells_map.v");
- else if (family_opt == "cyclonev")
- run("techmap -map +/intel/cyclonev/cells_map.v");
- else if (family_opt == "cyclone10")
- run("techmap -map +/intel/cyclone10/cells_map.v");
- else if (family_opt == "cycloneiv")
- run("techmap -map +/intel/cycloneiv/cells_map.v");
- else
- run("techmap -map +/intel/cycloneive/cells_map.v");
+ if (iopads || help_mode)
+ run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
+ run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 02:39:23 +0000