1 files changed, 51 insertions, 5 deletions
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index e09aafaa2..370e17f27 100644
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -50,10 +50,39 @@
 // model can be treated as always returning a defined result.
 
 (* abc9_box, lib_whitebox *)
-module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
+module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,
+    (* clkbuf_sink *) input CLK1,
+    input [4:0] B1ADDR, output B1DATA);
 
 reg [31:0] mem = 32'b0;
 
+`ifdef cyclonev
+specify
+    $setup(A1ADDR, posedge CLK1, 86);
+    $setup(A1DATA, posedge CLK1, 86);
+    $setup(A1EN, posedge CLK1, 86);
+
+    (B1ADDR[0] => B1DATA) = 487;
+    (B1ADDR[1] => B1DATA) = 475;
+    (B1ADDR[2] => B1DATA) = 382;
+    (B1ADDR[3] => B1DATA) = 284;
+    (B1ADDR[4] => B1DATA) = 96;
+endspecify
+`endif
+`ifdef arriav
+specify
+    $setup(A1ADDR, posedge CLK1, 62);
+    $setup(A1DATA, posedge CLK1, 62);
+    $setup(A1EN, posedge CLK1, 62);
+
+    (B1ADDR[0] => B1DATA) = 370;
+    (B1ADDR[1] => B1DATA) = 292;
+    (B1ADDR[2] => B1DATA) = 218;
+    (B1ADDR[3] => B1DATA) = 74;
+    (B1ADDR[4] => B1DATA) = 177;
+endspecify
+`endif
+`ifdef cyclone10gx
 // TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
 specify
     $setup(A1ADDR, posedge CLK1, 86);
@@ -66,6 +95,7 @@ specify
     (B1ADDR[3] => B1DATA) = 284;
     (B1ADDR[4] => B1DATA) = 96;
 endspecify
+`endif
 
 always @(posedge CLK1)
     if (A1EN) mem[A1ADDR] <= A1DATA;
@@ -83,7 +113,7 @@ module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 parameter CFG_ABITS = 10;
 parameter CFG_DBITS = 10;
 
-input CLK1;
+(* clkbuf_sink *) input CLK1;
 input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
 input [CFG_DBITS-1:0] A1DATA;
 input A1EN, B1EN;
@@ -91,12 +121,28 @@ output reg [CFG_DBITS-1:0] B1DATA;
 
 reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
 
+`ifdef cyclonev
+specify
+    $setup(A1ADDR, posedge CLK1, 125);
+    $setup(A1DATA, posedge CLK1, 97);
+    $setup(A1EN, posedge CLK1, 140);
+    $setup(B1ADDR, posedge CLK1, 125);
+    $setup(B1EN, posedge CLK1, 161);
+
+    if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;
+endspecify
+`endif
+`ifdef arriav
 specify
-    $setup(A1ADDR, posedge CLK1, 0);
-    $setup(A1DATA, posedge CLK1, 0);
+    $setup(A1ADDR, posedge CLK1, 97);
+    $setup(A1DATA, posedge CLK1, 74);
+    $setup(A1EN, posedge CLK1, 109);
+    $setup(B1ADDR, posedge CLK1, 97);
+    $setup(B1EN, posedge CLK1, 126);
 
-    if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
+    if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 787;
 endspecify
+`endif
 
 always @(posedge CLK1) begin
     if (A1EN)