1 files changed, 115 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index c40a4e02d..3b4628675 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -1,9 +1,11 @@
 `ifdef cyclonev
 `define LCELL cyclonev_lcell_comb
+`define MAC cyclonev_mac
 `define MLAB cyclonev_mlab_cell
 `endif
 `ifdef cyclone10gx
 `define LCELL cyclone10gx_lcell_comb
+`define MAC cyclone10gx_mac
 `define MLAB cyclone10gx_mlab_cell
 `endif
 
@@ -86,6 +88,8 @@ endmodule
 
 module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
 
+parameter _TECHMAP_CELLNAME_ = "";
+
 // Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
 // which takes in a hexadecimal string that could be used to initialise RAM.
 // In the vendor simulation models, this appears to work fine, but Quartus,
@@ -97,7 +101,7 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
 // or an undocumented way to get Quartus to initialise from mem_init0 is found.
 
 `MLAB #(
-    .logical_ram_name("MISTRAL_MLAB"),
+    .logical_ram_name(_TECHMAP_CELLNAME_),
     .logical_ram_depth(32),
     .logical_ram_width(1),
     .mixed_port_feed_through_mode("Dont Care"),
@@ -119,3 +123,113 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
 );
 
 endmodule
+
+
+module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+
+parameter _TECHMAP_CELLNAME_ = "";
+
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+input CLK1, A1EN, B1EN;
+output [CFG_DBITS-1:0] B1DATA;
+
+// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
+// you initialise the RAM cell via hex literals. If they were implemented.
+
+cyclonev_ram_block #(
+    .operation_mode("dual_port"),
+    .logical_ram_name(_TECHMAP_CELLNAME_),
+    .port_a_address_width(CFG_ABITS),
+    .port_a_data_width(CFG_DBITS),
+    .port_a_logical_ram_depth(2**CFG_ABITS),
+    .port_a_logical_ram_width(CFG_DBITS),
+    .port_a_first_address(0),
+    .port_a_last_address(2**CFG_ABITS - 1),
+    .port_a_first_bit_number(0),
+    .port_b_address_width(CFG_ABITS),
+    .port_b_data_width(CFG_DBITS),
+    .port_b_logical_ram_depth(2**CFG_ABITS),
+    .port_b_logical_ram_width(CFG_DBITS),
+    .port_b_first_address(0),
+    .port_b_last_address(2**CFG_ABITS - 1),
+    .port_b_first_bit_number(0),
+    .port_b_address_clock("clock0"),
+    .port_b_read_enable_clock("clock0")
+) _TECHMAP_REPLACE_ (
+    .portaaddr(A1ADDR),
+    .portadatain(A1DATA),
+    .portawe(A1EN),
+    .portbaddr(B1ADDR),
+    .portbdataout(B1DATA),
+    .portbre(B1EN),
+    .clk0(CLK1)
+);
+
+endmodule
+
+
+module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
+
+parameter A_SIGNED = 1;
+parameter B_SIGNED = 1;
+
+`MAC #(
+    .ax_width(27),
+    .signed_max(A_SIGNED ? "true" : "false"),
+    .ay_scan_in_width(27),
+    .signed_may(B_SIGNED ? "true" : "false"),
+    .result_a_width(54),
+    .operation_mode("M27x27")
+) _TECHMAP_REPLACE_ (
+    .ax(A),
+    .ay(B),
+    .resulta(Y)
+);
+
+endmodule
+
+
+module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
+
+parameter A_SIGNED = 1;
+parameter B_SIGNED = 1;
+
+`MAC #(
+    .ax_width(18),
+    .signed_max(A_SIGNED ? "true" : "false"),
+    .ay_scan_in_width(18),
+    .signed_may(B_SIGNED ? "true" : "false"),
+    .result_a_width(36),
+    .operation_mode("M18x18_FULL")
+) _TECHMAP_REPLACE_ (
+    .ax(A),
+    .ay(B),
+    .resulta(Y)
+);
+
+endmodule
+
+
+module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
+
+parameter A_SIGNED = 1;
+parameter B_SIGNED = 1;
+
+`MAC #(
+    .ax_width(9),
+    .signed_max(A_SIGNED ? "true" : "false"),
+    .ay_scan_in_width(9),
+    .signed_may(B_SIGNED ? "true" : "false"),
+    .result_a_width(18),
+    .operation_mode("M9x9")
+) _TECHMAP_REPLACE_ (
+    .ax(A),
+    .ay(B),
+    .resulta(Y)
+);
+
+endmodule