1 files changed, 69 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 99e1fe127..0d69e8c08 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -118,3 +118,72 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
 endmodule
+
+module RAM32X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+  parameter INIT = 32'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire \$DPO , \$SPO ;
+  \$__ABC_RAM32X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(\$DPO ), .SPO(\$SPO ),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
+    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
+  );
+  \$__ABC_LUTMUX dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+  \$__ABC_LUTMUX spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+endmodule
+
+module RAM64X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4, A5,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+  parameter INIT = 64'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire \$DPO , \$SPO ;
+  \$__ABC_RAM64X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(\$DPO ), .SPO(\$SPO ),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
+    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
+  );
+  \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+  \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+endmodule
+
+module \$__ABC_RAM128X1D (
+  output       DPO, SPO,
+  input        D,
+  input        WCLK,
+  input        WE,
+  input  [6:0] A, DPRA
+);
+  parameter INIT = 128'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire \$DPO , \$SPO ;
+  \$__ABC_RAM128X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(\$DPO ), .SPO(\$SPO ),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A(A),
+    .DPRA(DPRA)
+  );
+  \$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+  \$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+
+endmodule