diff options
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 04aa60f91..309ee500a 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -184,12 +184,12 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule -(* abc_box_id = 1, lib_whitebox *) +(* abc9_box_id = 1, lib_whitebox *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 2, lib_whitebox *) +(* abc9_box_id = 2, lib_whitebox *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule @@ -198,12 +198,12 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 4, lib_whitebox *) +(* abc9_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry *) + (* abc9_carry *) output [3:0] CO, output [3:0] O, - (* abc_carry *) + (* abc9_carry *) input CI, input CYINIT, input [3:0] DI, S @@ -240,9 +240,9 @@ endmodule // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 -(* abc_box_id=1001, lib_whitebox, abc9_flop *) +(* abc9_box_id=1001, lib_whitebox, abc9_flop *) module FDRE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -261,9 +261,9 @@ module FDRE ( wire \$currQ ; reg \$nextQ ; always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. @@ -287,9 +287,9 @@ module FDRE ( `endif endmodule -(* abc_box_id=1002, lib_whitebox, abc9_flop *) +(* abc9_box_id=1002, lib_whitebox, abc9_flop *) module FDRE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -300,9 +300,9 @@ module FDRE_1 ( wire \$currQ ; reg \$nextQ ; always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. @@ -323,9 +323,9 @@ module FDRE_1 ( `endif endmodule -(* abc_box_id=1003, lib_whitebox, abc9_flop *) +(* abc9_box_id=1003, lib_whitebox, abc9_flop *) module FDCE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -344,14 +344,14 @@ module FDCE ( wire \$currQ ; reg \$nextQ ; always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC_ASYNC box by abc_map.v + // using the $_ABC9_ASYNC box by abc9_map.v // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs @@ -374,9 +374,9 @@ module FDCE ( `endif endmodule -(* abc_box_id=1004, lib_whitebox, abc9_flop *) +(* abc9_box_id=1004, lib_whitebox, abc9_flop *) module FDCE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -387,14 +387,14 @@ module FDCE_1 ( wire \$currQ ; reg \$nextQ ; always @* if (CE) Q <= D; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC_ASYNC box by abc_map.v + // using the $_ABC9_ASYNC box by abc9_map.v // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs @@ -412,9 +412,9 @@ module FDCE_1 ( `endif endmodule -(* abc_box_id=1005, lib_whitebox, abc9_flop *) +(* abc9_box_id=1005, lib_whitebox, abc9_flop *) module FDPE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -433,14 +433,14 @@ module FDPE ( wire \$currQ ; reg \$nextQ ; always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC_ASYNC box by abc_map.v + // using the $_ABC9_ASYNC box by abc9_map.v // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs @@ -463,9 +463,9 @@ module FDPE ( `endif endmodule -(* abc_box_id=1006, lib_whitebox, abc9_flop *) +(* abc9_box_id=1006, lib_whitebox, abc9_flop *) module FDPE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -476,14 +476,14 @@ module FDPE_1 ( wire \$currQ ; reg \$nextQ ; always @* if (CE) Q <= D; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC_ASYNC box by abc_map.v + // using the $_ABC9_ASYNC box by abc9_map.v // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs @@ -501,9 +501,9 @@ module FDPE_1 ( `endif endmodule -(* abc_box_id=1007, lib_whitebox, abc9_flop *) +(* abc9_box_id=1007, lib_whitebox, abc9_flop *) module FDSE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -522,9 +522,9 @@ module FDSE ( wire \$currQ ; reg \$nextQ ; always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. @@ -548,9 +548,9 @@ module FDSE ( `endif endmodule -(* abc_box_id=1008, lib_whitebox, abc9_flop *) +(* abc9_box_id=1008, lib_whitebox, abc9_flop *) module FDSE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -561,9 +561,9 @@ module FDSE_1 ( wire \$currQ ; reg \$nextQ ; always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ; -`ifdef _ABC +`ifdef _ABC9 // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will // connect to the special `$currQ' wire. @@ -630,7 +630,7 @@ endmodule module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) + (* abc9_arrival=1153 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -653,7 +653,7 @@ endmodule module RAM64X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) + (* abc9_arrival=1153 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -676,7 +676,7 @@ endmodule module RAM128X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) + (* abc9_arrival=1153 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -696,7 +696,7 @@ endmodule module SRL16E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) + (* abc9_arrival=1472 *) output Q, input A0, A1, A2, A3, CE, (* clkbuf_sink *) @@ -744,9 +744,9 @@ endmodule module SRLC32E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) + (* abc9_arrival=1472 *) output Q, - (* abc_arrival=1114 *) + (* abc9_arrival=1114 *) output Q31, input [4:0] A, input CE, |