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-rw-r--r--techlibs/xilinx/cells_sim.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d705451fe..2947fe692 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -2160,13 +2160,13 @@ module DSP48E1 (
output reg [3:0] CARRYOUT,
output reg MULTSIGNOUT,
output OVERFLOW,
-`ifndef __ICARUS__
+`ifdef YOSYS
(* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
`endif
output reg signed [47:0] P,
output reg PATTERNBDETECT,
output reg PATTERNDETECT,
-`ifndef __ICARUS__
+`ifdef YOSYS
(* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
`endif
output [47:0] PCOUT,