1 files changed, 14 insertions, 5 deletions
diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v
index f3169ab4f..11168fe13 100644
--- a/techlibs/xilinx/drams_bb.v
+++ b/techlibs/xilinx/drams_bb.v
@@ -1,11 +1,20 @@
 
-module RAM32X1D (
+module RAM64X1D (
 	output DPO, SPO,
-	input  A0, A1, A2, A3, A4, D,
-	input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
-	input  WCLK, WE
+	input  D, WCLK, WE,
+	input  A0, A1, A2, A3, A4, A5,
+	input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
-	parameter INIT = 32'h0;
+	parameter INIT = 64'h0;
+	parameter IS_WCLK_INVERTED = 1'b0;
+endmodule
+
+module RAM128X1D (
+	output       DPO, SPO,
+	input        D, WCLK, WE,
+	input  [6:0] A, DPRA
+);
+	parameter INIT = 128'h0;
 	parameter IS_WCLK_INVERTED = 1'b0;
 endmodule