7 files changed, 0 insertions, 77 deletions
diff --git a/techlibs/xilinx/example_basys3/README b/techlibs/xilinx/example_basys3/README
deleted file mode 100644
index 85b6eab10..000000000
--- a/techlibs/xilinx/example_basys3/README
+++ /dev/null
@@ -1,16 +0,0 @@
-
-A simple example design, based on the Digilent BASYS3 board
-===========================================================
-
-Running Yosys:
-  yosys run_yosys.ys
-
-Running Vivado:
-  vivado -nolog -nojournal -mode batch -source run_vivado.tcl
-
-Programming board:
-  vivado -nolog -nojournal -mode batch -source run_prog.tcl
-
-All of the above:
-  bash run.sh
-
diff --git a/techlibs/xilinx/example_basys3/example.v b/techlibs/xilinx/example_basys3/example.v
deleted file mode 100644
index 2b01a22a8..000000000
--- a/techlibs/xilinx/example_basys3/example.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module example(CLK, LD);
-  input CLK;
-  output [15:0] LD;
-
-  wire clock;
-  reg [15:0] leds;
-
-  BUFG CLK_BUF (.I(CLK), .O(clock));
-  OBUF LD_BUF[15:0] (.I(leds), .O(LD));
-
-  parameter COUNTBITS = 26;
-  reg [COUNTBITS-1:0] counter;
-
-  always @(posedge CLK) begin
-    counter <= counter + 1;
-    if (counter[COUNTBITS-1])
-      leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
-    else
-      leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
-  end
-endmodule
diff --git a/techlibs/xilinx/example_basys3/example.xdc b/techlibs/xilinx/example_basys3/example.xdc
deleted file mode 100644
index c1fd0e925..000000000
--- a/techlibs/xilinx/example_basys3/example.xdc
+++ /dev/null
@@ -1,21 +0,0 @@
-
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5  } [get_ports CLK]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3  } [get_ports {LD[9]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3  } [get_ports {LD[10]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3  } [get_ports {LD[11]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3  } [get_ports {LD[12]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3  } [get_ports {LD[13]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1  } [get_ports {LD[14]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
-
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
-
diff --git a/techlibs/xilinx/example_basys3/run.sh b/techlibs/xilinx/example_basys3/run.sh
deleted file mode 100644
index 10f059103..000000000
--- a/techlibs/xilinx/example_basys3/run.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-yosys run_yosys.ys
-vivado -nolog -nojournal -mode batch -source run_vivado.tcl
-vivado -nolog -nojournal -mode batch -source run_prog.tcl
diff --git a/techlibs/xilinx/example_basys3/run_prog.tcl b/techlibs/xilinx/example_basys3/run_prog.tcl
deleted file mode 100644
index d711af840..000000000
--- a/techlibs/xilinx/example_basys3/run_prog.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-connect_hw_server
-open_hw_target [lindex [get_hw_targets] 0]
-set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
-program_hw_devices [lindex [get_hw_devices] 0]
diff --git a/techlibs/xilinx/example_basys3/run_vivado.tcl b/techlibs/xilinx/example_basys3/run_vivado.tcl
deleted file mode 100644
index c3b6a610e..000000000
--- a/techlibs/xilinx/example_basys3/run_vivado.tcl
+++ /dev/null
@@ -1,9 +0,0 @@
-read_xdc example.xdc
-read_edif example.edif
-link_design -part xc7a35tcpg236-1 -top example
-opt_design
-place_design
-route_design
-report_utilization
-report_timing
-write_bitstream -force example.bit
diff --git a/techlibs/xilinx/example_basys3/run_yosys.ys b/techlibs/xilinx/example_basys3/run_yosys.ys
deleted file mode 100644
index 4541826d3..000000000
--- a/techlibs/xilinx/example_basys3/run_yosys.ys
+++ /dev/null
@@ -1,2 +0,0 @@
-read_verilog example.v
-synth_xilinx -edif example.edif -top example