diff options
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index caeeb3266..6c598acf2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -478,13 +478,17 @@ struct SynthXilinxPass : public ScriptPass else if (abc9) { if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " - "will use timing for 'xc7' instead.\n", family.c_str()); + "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); + std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; + abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + abc9_opts += " -nomfs"; if (nowidelut) - run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; else - run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7.lut"; + run("abc9" + abc9_opts); } else { if (nowidelut) |