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-rw-r--r--techlibs/xilinx/synth_xilinx.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0058f626f..c10e42532 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass
{
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v");
+ Pass::call(design, "read_verilog +/xilinx/cells_box.v");
if (abc == "abc9")
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
else