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-rw-r--r--techlibs/xilinx7/cells.v53
-rw-r--r--techlibs/xilinx7/counter.v12
-rw-r--r--techlibs/xilinx7/counter_tb.v61
-rw-r--r--techlibs/xilinx7/example_mojo_counter/README10
-rw-r--r--techlibs/xilinx7/example_mojo_counter/example.sh67
-rw-r--r--techlibs/xilinx7/example_mojo_counter/example.ucf13
-rw-r--r--techlibs/xilinx7/example_mojo_counter/example.v14
-rw-r--r--techlibs/xilinx7/run_testbench.sh86
8 files changed, 0 insertions, 316 deletions
diff --git a/techlibs/xilinx7/cells.v b/techlibs/xilinx7/cells.v
deleted file mode 100644
index 8c8b9c759..000000000
--- a/techlibs/xilinx7/cells.v
+++ /dev/null
@@ -1,53 +0,0 @@
-module \$_DFF_P_ (D, C, Q);
-
- input D, C;
- output Q;
-
- FDRE fpga_dff (
- .D(D), .Q(Q), .C(C),
- .CE(1'b1), .R(1'b0)
- );
-
-endmodule
-
-module \$lut (I, O);
-
- parameter WIDTH = 0;
- parameter LUT = 0;
-
- input [WIDTH-1:0] I;
- output O;
-
- generate
- if (WIDTH == 1) begin:lut1
- LUT1 #(.INIT(LUT)) fpga_lut (.O(O),
- .I0(I[0]));
- end else
- if (WIDTH == 2) begin:lut2
- LUT2 #(.INIT(LUT)) fpga_lut (.O(O),
- .I0(I[0]), .I1(I[1]));
- end else
- if (WIDTH == 3) begin:lut3
- LUT3 #(.INIT(LUT)) fpga_lut (.O(O),
- .I0(I[0]), .I1(I[1]), .I2(I[2]));
- end else
- if (WIDTH == 4) begin:lut4
- LUT4 #(.INIT(LUT)) fpga_lut (.O(O),
- .I0(I[0]), .I1(I[1]), .I2(I[2]),
- .I3(I[3]));
- end else
- if (WIDTH == 5) begin:lut5
- LUT5 #(.INIT(LUT)) fpga_lut (.O(O),
- .I0(I[0]), .I1(I[1]), .I2(I[2]),
- .I3(I[3]), .I4(I[4]));
- end else
- if (WIDTH == 6) begin:lut6
- LUT6 #(.INIT(LUT)) fpga_lut (.O(O),
- .I0(I[0]), .I1(I[1]), .I2(I[2]),
- .I3(I[3]), .I4(I[4]), .I5(I[5]));
- end else begin:error
- wire TECHMAP_FAIL;
- end
- endgenerate
-
-endmodule
diff --git a/techlibs/xilinx7/counter.v b/techlibs/xilinx7/counter.v
deleted file mode 100644
index 72208bd80..000000000
--- a/techlibs/xilinx7/counter.v
+++ /dev/null
@@ -1,12 +0,0 @@
-module counter (clk, rst, en, count);
-
- input clk, rst, en;
- output reg [3:0] count;
-
- always @(posedge clk)
- if (rst)
- count <= 4'd0;
- else if (en)
- count <= count + 4'd1;
-
-endmodule
diff --git a/techlibs/xilinx7/counter_tb.v b/techlibs/xilinx7/counter_tb.v
deleted file mode 100644
index b6b64269e..000000000
--- a/techlibs/xilinx7/counter_tb.v
+++ /dev/null
@@ -1,61 +0,0 @@
-`timescale 1 ns / 1 ps
-
-module testbench;
-
-reg clk, en, rst;
-wire [3:0] count;
-
-counter uut_counter(
- .clk(clk),
- .count(count),
- .en(en),
- .rst(rst)
-);
-
-initial begin
- clk <= 0;
- forever begin
- #50;
- clk <= ~clk;
- end
-end
-
-initial begin
- @(posedge clk);
- forever begin
- @(posedge clk);
- $display("%d", count);
- end
-end
-
-initial begin
- rst <= 1; en <= 0; @(posedge clk);
- rst <= 1; en <= 0; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 1; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 1; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- $finish;
-end
-
-endmodule
diff --git a/techlibs/xilinx7/example_mojo_counter/README b/techlibs/xilinx7/example_mojo_counter/README
deleted file mode 100644
index 690a9d843..000000000
--- a/techlibs/xilinx7/example_mojo_counter/README
+++ /dev/null
@@ -1,10 +0,0 @@
-
-This is a simple example for Yosys synthesis targeting the Mojo FPGA
-development board [1, 2]. Simple script for xst-based synthesis (incl.
-generation of reference edif files) and uploading to the board can be
-found here [3].
-
-[1] http://embeddedmicro.com/tutorials/mojo
-[2] https://www.sparkfun.com/products/11953
-[3] http://svn.clifford.at/handicraft/2013/mojo/
-
diff --git a/techlibs/xilinx7/example_mojo_counter/example.sh b/techlibs/xilinx7/example_mojo_counter/example.sh
deleted file mode 100644
index 87af0ea31..000000000
--- a/techlibs/xilinx7/example_mojo_counter/example.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
-XILINX_PART=xc6slx9-2-tqg144
-
-../../../yosys - << EOT
-# read design
-read_verilog example.v
-
-# high-level synthesis
-hierarchy -check -top top
-proc; opt; fsm; opt; techmap; opt
-
-# mapping logic to LUTs using Berkeley ABC
-abc -lut 6; opt
-
-# map internal cells to FPGA cells
-techmap -map ../cells.v; opt
-
-# insert i/o buffers
-iopadmap -outpad OBUF I:O -inpad BUFGP O:I
-
-# write netlist
-write_edif synth.edif
-EOT
-
-cat > bitgen.ut <<- EOT
- -w
- -g DebugBitstream:No
- -g Binary:no
- -g CRC:Enable
- -g Reset_on_err:No
- -g ConfigRate:2
- -g ProgPin:PullUp
- -g TckPin:PullUp
- -g TdiPin:PullUp
- -g TdoPin:PullUp
- -g TmsPin:PullUp
- -g UnusedPin:PullDown
- -g UserID:0xFFFFFFFF
- -g ExtMasterCclk_en:No
- -g SPI_buswidth:1
- -g TIMER_CFG:0xFFFF
- -g multipin_wakeup:No
- -g StartUpClk:CClk
- -g DONE_cycle:4
- -g GTS_cycle:5
- -g GWE_cycle:6
- -g LCK_cycle:NoWait
- -g Security:None
- -g DonePipe:No
- -g DriveDone:No
- -g en_sw_gsr:No
- -g drive_awake:No
- -g sw_clk:Startupclk
- -g sw_gwe_cycle:5
- -g sw_gts_cycle:4
-EOT
-
-$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
-$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
-$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
-$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
-$XILINX_DIR/bin/lin64/bitgen -f bitgen.ut placed.ncd example.bit constraints.pcf
-
diff --git a/techlibs/xilinx7/example_mojo_counter/example.ucf b/techlibs/xilinx7/example_mojo_counter/example.ucf
deleted file mode 100644
index 591cbe76f..000000000
--- a/techlibs/xilinx7/example_mojo_counter/example.ucf
+++ /dev/null
@@ -1,13 +0,0 @@
-NET "clk" TNM_NET = clk;
-TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
-
-NET "clk" LOC = P56;
-
-NET "led_0" LOC = P134;
-NET "led_1" LOC = P133;
-NET "led_2" LOC = P132;
-NET "led_3" LOC = P131;
-NET "led_4" LOC = P127;
-NET "led_5" LOC = P126;
-NET "led_6" LOC = P124;
-NET "led_7" LOC = P123;
diff --git a/techlibs/xilinx7/example_mojo_counter/example.v b/techlibs/xilinx7/example_mojo_counter/example.v
deleted file mode 100644
index 8e79942e2..000000000
--- a/techlibs/xilinx7/example_mojo_counter/example.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module top(clk, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
-
-input clk;
-output led_7, led_6, led_5, led_4;
-output led_3, led_2, led_1, led_0;
-
-reg [31:0] counter;
-
-always @(posedge clk)
- counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
-
-assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
-
-endmodule
diff --git a/techlibs/xilinx7/run_testbench.sh b/techlibs/xilinx7/run_testbench.sh
deleted file mode 100644
index b4251f496..000000000
--- a/techlibs/xilinx7/run_testbench.sh
+++ /dev/null
@@ -1,86 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/
-
-../../yosys - <<- EOT
- # read design
- read_verilog counter.v
-
- # high-level synthesis
- hierarchy -check -top counter
- proc; opt; fsm; opt; techmap; opt
-
- # mapping logic to LUTs using Berkeley ABC
- abc -lut 6; opt
-
- # map internal cells to FPGA cells
- techmap -map cells.v; opt
-
- # write netlist
- write_verilog -noattr testbench_synth.v
- write_edif testbench_synth.edif
-EOT
-
-iverilog -o testbench_gold counter_tb.v counter.v
-iverilog -o testbench_gate counter_tb.v testbench_synth.v \
- $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
-
-./testbench_gold > testbench_gold.txt
-./testbench_gate > testbench_gate.txt
-
-if diff -u testbench_gold.txt testbench_gate.txt; then
- set +x; echo; echo; banner " PASS "
-else
- exit 1
-fi
-
-if [ "$*" = "-map" ]; then
- set -x
-
- cat > testbench_synth.ut <<- EOT
- -w
- -g DebugBitstream:No
- -g Binary:no
- -g CRC:Enable
- -g Reset_on_err:No
- -g ConfigRate:2
- -g ProgPin:PullUp
- -g TckPin:PullUp
- -g TdiPin:PullUp
- -g TdoPin:PullUp
- -g TmsPin:PullUp
- -g UnusedPin:PullDown
- -g UserID:0xFFFFFFFF
- -g ExtMasterCclk_en:No
- -g SPI_buswidth:1
- -g TIMER_CFG:0xFFFF
- -g multipin_wakeup:No
- -g StartUpClk:CClk
- -g DONE_cycle:4
- -g GTS_cycle:5
- -g GWE_cycle:6
- -g LCK_cycle:NoWait
- -g Security:None
- -g DonePipe:No
- -g DriveDone:No
- -g en_sw_gsr:No
- -g drive_awake:No
- -g sw_clk:Startupclk
- -g sw_gwe_cycle:5
- -g sw_gts_cycle:4
- EOT
-
- $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif
- $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth
- $XILINX_DIR/bin/lin64/map -p xc7k70t-fbg676-1 -w -o testbench_mapped.ncd testbench_synth prffile.pcf
- $XILINX_DIR/bin/lin64/par -w testbench_mapped.ncd testbench_synth.ncd prffile.pcf
- $XILINX_DIR/bin/lin64/bitgen -f testbench_synth.ut testbench_synth.ncd
-fi
-
-if [ "$*" = "-clean" ]; then
- rm -rf netlist.lst _xmsgs/ prffile.pcf
- rm -f testbench_{synth,gold,gate,mapped}*
-fi
-
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-25 02:20:40 +0000