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-rw-r--r--techlibs/greenpak4/Makefile.inc1
-rw-r--r--techlibs/greenpak4/cells_latch.v15
-rw-r--r--techlibs/greenpak4/cells_map.v52
-rw-r--r--techlibs/greenpak4/cells_sim.v96
-rw-r--r--techlibs/greenpak4/greenpak4_dffinv.cc21
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc3
6 files changed, 183 insertions, 5 deletions
diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 1c9871e2f..7482af6c6 100644
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/greenpak4/synth_greenpak4.o
OBJS += techlibs/greenpak4/greenpak4_counters.o
OBJS += techlibs/greenpak4/greenpak4_dffinv.o
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
diff --git a/techlibs/greenpak4/cells_latch.v b/techlibs/greenpak4/cells_latch.v
new file mode 100644
index 000000000..2ccdd2031
--- /dev/null
+++ b/techlibs/greenpak4/cells_latch.v
@@ -0,0 +1,15 @@
+module $_DLATCH_P_(input E, input D, output Q);
+ GP_DLATCH _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(!E),
+ .Q(Q)
+ );
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+ GP_DLATCH _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(E),
+ .Q(Q)
+ );
+endmodule
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index 111a77a14..f8fb2569a 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -50,6 +50,58 @@ module GP_DFFRI(input D, CLK, nRST, output reg nQ);
);
endmodule
+module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSR #(
+ .INIT(INIT),
+ .SRMODE(1'b1),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nSET),
+ .Q(Q)
+ );
+endmodule
+
+module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSR #(
+ .INIT(INIT),
+ .SRMODE(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nRST),
+ .Q(Q)
+ );
+endmodule
+
+module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSRI #(
+ .INIT(INIT),
+ .SRMODE(1'b1),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nSET),
+ .nQ(nQ)
+ );
+endmodule
+
+module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSRI #(
+ .INIT(INIT),
+ .SRMODE(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nRST),
+ .nQ(nQ)
+ );
+endmodule
+
module GP_OBUFT(input IN, input OE, output OUT);
GP_IOBUF _TECHMAP_REPLACE_ (
.IN(IN),
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 80746be0f..1b899e8e8 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -18,7 +18,11 @@ endmodule
module GP_ABUF(input wire IN, output wire OUT);
assign OUT = IN;
-
+
+ //must be 1, 5, 20, 50
+ //values >1 only available with Vdd > 2.7V
+ parameter BANDWIDTH_KHZ = 1;
+
//cannot simulate mixed signal IP
endmodule
@@ -240,6 +244,92 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
end
endmodule
+module GP_DLATCH(input D, input nCLK, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHI(input D, input nCLK, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nRST)
+ Q <= 1'b0;
+ else if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nRST)
+ nQ <= 1'b1;
+ else if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nSET)
+ Q <= 1'b1;
+ else if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nSET)
+ nQ <= 1'b0;
+ else if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ parameter[0:0] SRMODE = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nSR)
+ Q <= SRMODE;
+ else if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ parameter[0:0] SRMODE = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nSR)
+ nQ <= ~SRMODE;
+ else if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
module GP_EDGEDET(input IN, output reg OUT);
parameter EDGE_DIRECTION = "RISING";
@@ -326,6 +416,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
endmodule
+module GP_PWRDET(output reg VDD_LOW);
+ initial VDD_LOW = 0;
+endmodule
+
module GP_POR(output reg RST_DONE);
parameter POR_TIME = 500;
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index ff63958e6..7d9d7d5b0 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
void invert_gp_dff(Cell *cell, bool invert_input)
{
string cell_type = cell->type.str();
+ bool cell_type_latch = cell_type.find("LATCH") != string::npos;
bool cell_type_i = cell_type.find('I') != string::npos;
bool cell_type_r = cell_type.find('R') != string::npos;
bool cell_type_s = cell_type.find('S') != string::npos;
@@ -79,25 +80,28 @@ void invert_gp_dff(Cell *cell, bool invert_input)
cell_type_i = true;
}
- cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+ if(cell_type_latch)
+ cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+ else
+ cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
}
struct Greenpak4DffInvPass : public Pass {
- Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFFs") { }
+ Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
virtual void help()
{
log("\n");
log(" greenpak4_dffinv [options] [selection]\n");
log("\n");
- log("Merge GP_INV cells with GP_DFF* cells.\n");
+ log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- log_header(design, "Executing GREENPAK4_DFFINV pass (merge synchronous set/reset into FF cells).\n");
+ log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -120,6 +124,15 @@ struct Greenpak4DffInvPass : public Pass {
gp_dff_types.insert("\\GP_DFFSR");
gp_dff_types.insert("\\GP_DFFSRI");
+ gp_dff_types.insert("\\GP_DLATCH");
+ gp_dff_types.insert("\\GP_DLATCHI");
+ gp_dff_types.insert("\\GP_DLATCHR");
+ gp_dff_types.insert("\\GP_DLATCHRI");
+ gp_dff_types.insert("\\GP_DLATCHS");
+ gp_dff_types.insert("\\GP_DLATCHSI");
+ gp_dff_types.insert("\\GP_DLATCHSR");
+ gp_dff_types.insert("\\GP_DLATCHSRI");
+
for (auto module : design->selected_modules())
{
SigMap sigmap(module);
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 10e2a1498..be12ab495 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -36,6 +36,8 @@ struct SynthGreenPAK4Pass : public ScriptPass
log(" synth_greenpak4 [options]\n");
log("\n");
log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
+ log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
+ log("place-and-route.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
@@ -159,6 +161,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("memory_map");
run("opt -undriven -fine");
run("techmap");
+ run("techmap -map +/greenpak4/cells_latch.v");
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
run("opt -fast");
if (retime || help_mode)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-30 00:39:05 +0000