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* Merge pull request #3727 from YosysHQ/micko/pll_bramMiodrag Milanović2023-04-145-124/+325
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| * Add PLL and EBR related primitivesMiodrag Milanovic2023-04-105-124/+325
* | fabulous: Add support for LUT6sgatecat2023-04-122-1/+38
* | gowin: Add serialization/deserialization primitivesYRabbit2023-04-121-0/+244
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* ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB modelgatecat2023-04-061-160/+30
* Add more DFF typesMiodrag Milanovic2023-04-065-48/+102
* Added proper simulation model for CCU2DMiodrag Milanovic2023-04-061-15/+35
* Generate TRELLIS_DPR16X4 for lutramMiodrag Milanovic2023-04-063-21/+72
* machxo2: Initial support for carry chains (CCU2D)Miodrag Milanovic2023-04-064-5/+127
* Update Xilinx cell definitions, fixes #3699Miodrag Milanovic2023-03-233-6/+16
* Start unification effort for machxo2 and ecp5Miodrag Milanovic2023-03-204-31/+23
* Add additional iopad_external_pin attributesMiodrag Milanovic2023-03-201-4/+22
* Add iopad_external_pin to some basic io primitivesMiodrag Milanovic2023-03-202-12/+13
* insert IO buffers for ECP5, off by defaultMiodrag Milanovic2023-03-201-1/+14
* ice40: Fix path delay definitionsStefan Riesenberger2023-03-101-14/+14
* Merge pull request #3688 from pu-cc/gatemate-reginitN. Engelhardt2023-03-013-8/+16
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| * gatemate: Enable register initializationPatrick Urban2023-02-153-8/+16
* | Merge pull request #3663 from uis246/masterMiodrag Milanović2023-02-281-0/+17
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| * | gowin: Add new types of oscillatoruis2023-02-061-0/+17
* | | Merge pull request #3652 from martell/elvdsMiodrag Milanović2023-02-281-0/+8
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| * | | gowin: Add support for emulated differential outputmartell2023-01-291-0/+8
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* | | fabulous: Add support for mapping carry chainsgatecat2023-02-274-2/+93
* | | Check DREG attributeOliver Keszöcze2023-02-171-1/+1
* | | fabulous: Add CLK to BRAM interface primitivesgatecat2023-02-161-3/+3
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* | gatemate: Update CC_PLL parametersPatrick Urban2023-02-141-0/+3
* | gatemate: Add CC_USR_RSTN primitivePatrick Urban2023-02-141-0/+6
* | gatemate: Ensure compatibility of LVDS ports with VHDLPatrick Urban2023-02-141-12/+12
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* Merge pull request #3630 from yrabbit/gw1n4c-pllMiodrag Milanović2023-01-181-0/+47
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| * gowin: add a new type of PLL - PLLVRYRabbit2023-01-111-0/+47
* | Merge pull request #3537 from jix/xpropJannis Harder2023-01-112-10/+60
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| * Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-302-1/+38
| * simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
| * simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
| * simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
| * satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-301-4/+11
* | nexus: Fix BRAM write enable in PDP modegatecat2023-01-041-2/+2
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* fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-171-0/+32
* fabulous: improvements to the passgatecat2022-11-176-139/+199
* fabulous: Unify and update primitivesgatecat2022-11-173-852/+356
* Introduce RegFile mappingsTaoBi222022-11-174-2/+95
* Replace synth call with components, reintroduce flags and correct vpr flag im...TaoBi222022-11-171-4/+76
* Reorder operations to load in primitive library before hierarchy passTaoBi222022-11-171-5/+6
* Add plib flag to specify custom primitive library pathTaoBi222022-11-171-2/+14
* Remove flattening from FABulous passTaoBi222022-11-171-11/+2
* Remove ALL currently unused flags (some to be reintroduced later and passed t...TaoBi222022-11-171-82/+3
* Add synth_fabulous ScriptPassTaoBi222022-11-178-0/+1282
* simlib: Simplify recently changed $mux modelJannis Harder2022-10-281-4/+2
* Merge pull request #3526 from jix/mux-simlib-evalJannis Harder2022-10-241-4/+1
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| * Consistent $mux undef handlingJannis Harder2022-10-241-4/+1
* | Add smtmap.v describing the smt2 backend's behavior for undef bitsJannis Harder2022-10-202-0/+29
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