23 files changed, 280 insertions, 46 deletions

diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v
index 95f5d59c5..9f647cbef 100755
--- a/techlibs/achronix/speedster22i/cells_map.v
+++ b/techlibs/achronix/speedster22i/cells_map.v
@@ -32,7 +32,7 @@ endmodule
 // > end buffers <
 
 // > Look-Up table <
-// > VT: I still think Achronix folks would have choosen a better \
+// > VT: I still think Achronix folks would have chosen a better \
 // >     logic architecture.
 // LUT Map
 module \$lut (A, Y);
@@ -43,30 +43,30 @@ module \$lut (A, Y);
    generate
       if (WIDTH == 1) begin
 	   // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
-         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
            (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
       end else
       if (WIDTH == 2) begin
-              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
       end else
       if(WIDTH == 3) begin
-	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ 
+	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
       end else
       if(WIDTH == 4) begin
-             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ 
+             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
       end else
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
-endmodule 
+endmodule
 // > end LUT <
 
 // > Flops <
 // DFF flop
 module  \$_DFF_P_ (input D, C, output Q);
-   DFF _TECHMAP_REPLACE_ 
+   DFF _TECHMAP_REPLACE_
      (.q(Q), .d(D), .ck(C));
-endmodule 
+endmodule
 
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 92b10781d..3642e3bd3 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -108,7 +108,7 @@ struct SynthAchronixPass : public ScriptPass {
     extra_args(args, argidx, design);
 
     if (!design->full_selection())
-      log_cmd_error("This comannd only operates on fully selected designs!\n");
+      log_cmd_error("This command only operates on fully selected designs!\n");
 
     log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
     log_push();
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index f37b5e7e9..67cf9cf10 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -1,6 +1,7 @@
 
 OBJS += techlibs/anlogic/synth_anlogic.o
 OBJS += techlibs/anlogic/anlogic_eqn.o
+OBJS += techlibs/anlogic/anlogic_determine_init.o
 
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
@@ -8,3 +9,4 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
new file mode 100644
index 000000000..34b1d4f8a
--- /dev/null
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -0,0 +1,72 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct AnlogicDetermineInitPass : public Pass {
+	AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    anlogic_determine_init [selection]\n");
+		log("\n");
+		log("Determine the init value of cells that doesn't allow unknown init value.\n");
+		log("\n");
+	}
+
+	Const determine_init(Const init)
+	{
+		for (int i = 0; i < GetSize(init); i++) {
+			if (init[i] != State::S0 && init[i] != State::S1)
+				init[i] = State::S0;
+		}
+
+		return init;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
+
+		extra_args(args, args.size(), design);
+
+		size_t cnt = 0;
+		for (auto module : design->selected_modules())
+		{
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type == "\\EG_LOGIC_DRAM16X4")
+				{
+					cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
+					cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
+					cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
+					cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
+					cnt++;
+				}
+			}
+		}
+		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+	}
+} AnlogicDetermineInitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index f54a81dcc..cfc743a4b 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -1,19 +1,19 @@
-module  \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
-module  \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(1'b0)); endmodule
+module  \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(1'b0)); endmodule
 
-module  \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module  \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module  \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
 
 module \$_DLATCH_N_ (E, D, Q);
   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/dram_init_16x4.vh
new file mode 100644
index 000000000..32fb1578c
--- /dev/null
+++ b/techlibs/anlogic/dram_init_16x4.vh
@@ -0,0 +1,16 @@
+.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
+	  INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
+	  INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
+	  INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
+.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
+	  INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
+	  INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
+	  INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
+.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
+	  INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
+	  INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
+	  INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
+.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
+	  INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
+	  INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
+	  INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
index eb94775ae..4e903c0a2 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/drams.txt
@@ -1,5 +1,5 @@
 bram $__ANLOGIC_DRAM16X4
-  init 0
+  init 1
   abits 4
   dbits 4
   groups 2
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v
index 87cbb6a45..084e2a25f 100644
--- a/techlibs/anlogic/drams_map.v
+++ b/techlibs/anlogic/drams_map.v
@@ -1,4 +1,5 @@
 module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0]INIT = 64'bx;
 	input CLK1;
 
 	input [3:0] A1ADDR;
@@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	input [3:0] B1DATA;
 	input B1EN;
 
-	EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
+	EG_LOGIC_DRAM16X4 #(
+		`include "dram_init_16x4.vh"
+	) _TECHMAP_REPLACE_ (
 		.di(B1DATA),
 		.waddr(B1ADDR),
 		.wclk(CLK1),
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 9c44599ea..620bf3965 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -119,7 +119,7 @@ struct SynthAnlogicPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ANLOGIC pass.\n");
 		log_push();
@@ -154,6 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("memory_bram -rules +/anlogic/drams.txt");
 			run("techmap -map +/anlogic/drams_map.v");
+			run("anlogic_determine_init");
 		}
 
 		if (check_label("fine"))
@@ -170,6 +171,7 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("dffsr2dff");
 			run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
+			run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 		}
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 70074f653..0e05620bc 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -26,5 +26,5 @@ $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
 $(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
 $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
 $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
+$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
-
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
new file mode 100644
index 000000000..8aa1eb957
--- /dev/null
+++ b/techlibs/common/cmp2lut.v
@@ -0,0 +1,105 @@
+// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
+// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
+// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
+// cannot be optimized further.
+//
+// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
+// with n <= k inputs should be techmapped in this way, because this shortens the critical path
+// from n to 1 by avoiding carry chains.
+
+(* techmap_celltype = "$eq $ne $lt $le $gt $ge" *)
+module _90_lut_cmp_ (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+parameter _TECHMAP_CELLTYPE_ = "";
+
+parameter _TECHMAP_CONSTMSK_A_ = 0;
+parameter _TECHMAP_CONSTVAL_A_ = 0;
+parameter _TECHMAP_CONSTMSK_B_ = 0;
+parameter _TECHMAP_CONSTVAL_B_ = 0;
+
+function automatic integer gen_lut;
+	input integer width;
+	input integer operation;
+	input integer swap;
+	input integer sign;
+	input integer operand;
+	integer n, i_var, i_cst, lhs, rhs, o_bit;
+	begin
+		gen_lut = width'b0;
+		for (n = 0; n < (1 << width); n++) begin
+			if (sign)
+				i_var = n[width-1:0];
+			else
+				i_var = n;
+			i_cst = operand;
+			if (swap) begin
+				lhs = i_cst;
+				rhs = i_var;
+			end else begin
+				lhs = i_var;
+				rhs = i_cst;
+			end
+			if (operation == 0)
+				o_bit = (lhs <  rhs);
+			if (operation == 1)
+				o_bit = (lhs <= rhs);
+			if (operation == 2)
+				o_bit = (lhs >  rhs);
+			if (operation == 3)
+				o_bit = (lhs >= rhs);
+			if (operation == 4)
+				o_bit = (lhs == rhs);
+			if (operation == 5)
+				o_bit = (lhs != rhs);
+			gen_lut = gen_lut | (o_bit << n);
+		end
+	end
+endfunction
+
+generate
+	if (_TECHMAP_CELLTYPE_ == "$lt")
+		localparam operation = 0;
+	if (_TECHMAP_CELLTYPE_ == "$le")
+		localparam operation = 1;
+	if (_TECHMAP_CELLTYPE_ == "$gt")
+		localparam operation = 2;
+	if (_TECHMAP_CELLTYPE_ == "$ge")
+		localparam operation = 3;
+	if (_TECHMAP_CELLTYPE_ == "$eq")
+		localparam operation = 4;
+	if (_TECHMAP_CELLTYPE_ == "$ne")
+		localparam operation = 5;
+
+	if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
+		wire _TECHMAP_FAIL_ = 1;
+	else if (&_TECHMAP_CONSTMSK_B_)
+		\$lut #(
+			.WIDTH(A_WIDTH),
+			.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
+		) _TECHMAP_REPLACE_ (
+			.A(A),
+			.Y(Y)
+		);
+	else if (&_TECHMAP_CONSTMSK_A_)
+		\$lut #(
+			.WIDTH(B_WIDTH),
+			.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
+		) _TECHMAP_REPLACE_ (
+			.A(B),
+			.Y(Y)
+		);
+	else
+		wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 897f37dbb..86fb4d6c6 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -153,7 +153,7 @@ struct PrepPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing PREP pass.\n");
 		log_push();
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index efb214759..ccfa76e02 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -51,6 +51,9 @@ struct SynthPass : public ScriptPass
 		log("    -encfile <file>\n");
 		log("        passed to 'fsm_recode' via 'fsm'\n");
 		log("\n");
+		log("    -lut <k>\n");
+		log("        perform synthesis for a k-LUT architecture.\n");
+		log("\n");
 		log("    -nofsm\n");
 		log("        do not run FSM optimization\n");
 		log("\n");
@@ -80,6 +83,7 @@ struct SynthPass : public ScriptPass
 
 	string top_module, fsm_opts, memory_opts;
 	bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
+	int lut;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -89,6 +93,7 @@ struct SynthPass : public ScriptPass
 
 		autotop = false;
 		flatten = false;
+		lut = 0;
 		noalumacc = false;
 		nofsm = false;
 		noabc = false;
@@ -130,6 +135,10 @@ struct SynthPass : public ScriptPass
 				flatten = true;
 				continue;
 			}
+			if (args[argidx] == "-lut") {
+				lut = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-nofsm") {
 				nofsm = true;
 				continue;
@@ -155,7 +164,7 @@ struct SynthPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH pass.\n");
 		log_push();
@@ -186,19 +195,23 @@ struct SynthPass : public ScriptPass
 		{
 			run("proc");
 			if (help_mode || flatten)
-				run("flatten", "(if -flatten)");
+				run("flatten", "  (if -flatten)");
 			run("opt_expr");
 			run("opt_clean");
 			run("check");
 			run("opt");
 			run("wreduce");
+			if (help_mode)
+				run("techmap -map +/cmp2lut.v", " (if -lut)");
+			else
+				run(stringf("techmap -map +/cmp2lut.v -D LUT_WIDTH=%d", lut));
 			if (!noalumacc)
-				run("alumacc");
+				run("alumacc", "  (unless -noalumacc)");
 			if (!noshare)
-				run("share");
+				run("share", "    (unless -noshare)");
 			run("opt");
 			if (!nofsm)
-				run("fsm" + fsm_opts);
+				run("fsm" + fsm_opts, "      (unless -nofsm)");
 			run("opt -fast");
 			run("memory -nomap" + memory_opts);
 			run("opt_clean");
@@ -210,12 +223,33 @@ struct SynthPass : public ScriptPass
 			run("memory_map");
 			run("opt -full");
 			run("techmap");
+			if (help_mode)
+			{
+				run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
+				run("clean; opt_lut", "           (if -noabc and -lut)");
+			}
+			else if (noabc && lut)
+			{
+				run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
+				run("clean; opt_lut");
+			}
 			run("opt -fast");
 
 			if (!noabc) {
 		#ifdef YOSYS_ENABLE_ABC
-				run("abc -fast");
-				run("opt -fast");
+				if (help_mode)
+				{
+					run("abc -fast", "       (unless -noabc, unless -lut)");
+					run("abc -fast -lut k", "(unless -noabc, if -lut)");
+				}
+				else
+				{
+					if (lut)
+						run(stringf("abc -fast -lut %d", lut));
+					else
+						run("abc -fast");
+				}
+				run("opt -fast", "       (unless -noabc)");
 		#endif
 			}
 		}
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index a5dac3566..810380d4a 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -111,7 +111,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
 		log_push();
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index b5ed93be4..dd9e3dab7 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -117,7 +117,7 @@ struct SynthEasicPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_EASIC pass.\n");
 		log_push();
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 057f9d737..425d62d24 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -484,7 +484,7 @@ module DCUA(
 	parameter D_XGE_MODE = "0b0";
 
 // These parameters don't do anything but are
-// needed for compatability with Diamond
+// needed for compatibility with Diamond
 	parameter D_TX_MAX_RATE = "2.5";
 	parameter D_RX_MAX_RATE = "2.5";
 	parameter CH0_TXAMPLITUDE = "0d1300";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 825e131c4..2e9176a84 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -189,7 +189,7 @@ struct SynthEcp5Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ECP5 pass.\n");
 		log_push();
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index e3d924e26..9700b3898 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -109,7 +109,7 @@ struct SynthGowinPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_GOWIN pass.\n");
 		log_push();
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index b91d5273a..eeb001b46 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -120,7 +120,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
 			log_cmd_error("Invalid part name: '%s'\n", part.c_str());
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c2aed873b..f900453e8 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -198,7 +198,7 @@ struct SynthIce40Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
@@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -run coarse");
+			run("synth -lut 4 -run coarse");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v
index 5ecdabcfc..fa27c2c8e 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel/cyclonev/cells_sim.v
@@ -54,7 +54,7 @@ module cyclonev_lcell_comb
    // Internal variables
    // Sub mask for fragmented LUTs
    wire [15:0] mask_a, mask_b, mask_c, mask_d;
-   // Independant output for fragmented LUTs
+   // Independent output for fragmented LUTs
    wire        output_0, output_1, output_2, output_3;
    // Extended mode uses mux to define the output
    wire        mux_0, mux_1;
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 2676ea657..62b3cd0e2 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -118,7 +118,7 @@ struct SynthSf2Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_SF2 pass.\n");
 		log_push();
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b27c08529..6c11d885d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -178,7 +178,7 @@ struct SynthXilinxPass : public Pass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		bool active = run_from.empty();