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-rw-r--r--techlibs/common/Makefile.inc1
-rw-r--r--techlibs/common/mul2dsp.v237
-rw-r--r--techlibs/ecp5/Makefile.inc1
-rw-r--r--techlibs/ecp5/dsp_map.v10
-rw-r--r--techlibs/ecp5/synth_ecp5.cc33
-rw-r--r--techlibs/xilinx/cells_map.v41
-rw-r--r--techlibs/xilinx/synth_xilinx.cc18
7 files changed, 336 insertions, 5 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 0e05620bc..e6d1c2f29 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -28,3 +28,4 @@ $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
+$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
new file mode 100644
index 000000000..ece45db79
--- /dev/null
+++ b/techlibs/common/mul2dsp.v
@@ -0,0 +1,237 @@
+// From Eddie Hung
+// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220
+// revised by Andre DeHon
+// further revised by David Shah
+`ifndef DSP_A_MAXWIDTH
+`define DSP_A_MAXWIDTH 18
+`endif
+`ifndef DSP_A_MAXWIDTH
+`define DSP_B_MAXWIDTH 25
+`endif
+
+`ifndef ADDER_MINWIDTH
+`define ADDER_MINWIDTH AAA
+`endif
+
+`ifndef DSP_NAME
+`define DSP_NAME M18x25
+`endif
+
+`define MAX(a,b) (a > b ? a : b)
+`define MIN(a,b) (a < b ? a : b)
+
+(* techmap_celltype = "$mul" *)
+module \$mul (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ input [A_WIDTH-1:0] A;
+ input [B_WIDTH-1:0] B;
+ output [Y_WIDTH-1:0] Y;
+
+ wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+ generate
+ if (A_WIDTH<B_WIDTH) begin
+ generate
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) mul_slice (
+ .A(A),
+ .B(B),
+ .Y(Y[Y_WIDTH-1:0])
+ );
+ endgenerate
+ end
+ else begin
+ generate
+ \$__mul_gen #(
+ .A_SIGNED(B_SIGNED),
+ .B_SIGNED(A_SIGNED),
+ .A_WIDTH(B_WIDTH),
+ .B_WIDTH(A_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) mul_slice (
+ .A(B),
+ .B(A),
+ .Y(Y[Y_WIDTH-1:0])
+ );
+ endgenerate
+ end
+ endgenerate
+endmodule
+
+module \$__mul_gen (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ input [A_WIDTH-1:0] A;
+ input [B_WIDTH-1:0] B;
+ output [Y_WIDTH-1:0] Y;
+
+ wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+ generate
+ if (A_WIDTH > `DSP_A_MAXWIDTH) begin
+ localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH;
+ localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0);
+ wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1];
+ wire [Y_WIDTH-1:0] partial_sum [n-2:0];
+
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(`DSP_A_MAXWIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH)
+ ) mul_slice_first (
+ .A(A[`DSP_A_MAXWIDTH-1:0]),
+ .B(B),
+ .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0])
+ );
+ assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0;
+
+ genvar i;
+ generate
+ for (i = 1; i < n-1; i=i+1) begin:slice
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(`DSP_A_MAXWIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH)
+ ) mul_slice (
+ .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]),
+ .B(B),
+ .Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0])
+ );
+ //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1];
+ assign partial_sum[i] = {
+ partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]
+ + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)],
+ partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0]
+ };
+ end
+ endgenerate
+
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH),
+ ) mul_slice_last (
+ .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]),
+ .B(B),
+ .Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0])
+ );
+ //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2];
+ assign Y = {
+ partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0]
+ + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)],
+ partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0]
+ };
+ end
+ else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
+ localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH;
+ localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0);
+ wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1];
+ wire [Y_WIDTH-1:0] partial_sum [n-2:0];
+
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(`DSP_B_MAXWIDTH),
+ .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH)
+ ) mul_first (
+ .A(A),
+ .B(B[`DSP_B_MAXWIDTH-1:0]),
+ .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0])
+ );
+ assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0;
+
+ genvar i;
+ generate
+ for (i = 1; i < n-1; i=i+1) begin:slice
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(`DSP_B_MAXWIDTH),
+ .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH)
+ ) mul (
+ .A(A),
+ .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]),
+ .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0])
+ );
+ //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1];
+ // was:
+ //assign partial_sum[i] = {
+ // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],
+ // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)],
+ // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0]
+ assign partial_sum[i] = {
+ partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]
+ + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)],
+ partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0]
+ };
+ end
+ endgenerate
+
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH),
+ .Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)
+ ) mul_last (
+ .A(A),
+ .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]),
+ .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0])
+ );
+ // AMD: this came comment out -- looks closer to right answer
+ //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2];
+ // was (looks broken)
+ //assign Y = {
+ // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],
+ // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)],
+ // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0]
+ assign Y = {
+ partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]
+ + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)],
+ partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0]
+ };
+ end
+ else begin
+ wire [A_WIDTH+B_WIDTH-1:0] out;
+ wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy;
+ wire Asign, Bsign;
+ assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
+ assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0);
+ `DSP_NAME _TECHMAP_REPLACE_ (
+ .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }),
+ .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }),
+ .OUT({dummy, out})
+ );
+ if (Y_WIDTH < A_WIDTH+B_WIDTH)
+ assign Y = out[Y_WIDTH-1:0];
+ else begin
+ wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0);
+ assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] };
+ end
+ end
+ endgenerate
+endmodule
+
+
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index ff39ba4fe..a2f5cadee 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -10,6 +10,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
new file mode 100644
index 000000000..5f7755afb
--- /dev/null
+++ b/techlibs/ecp5/dsp_map.v
@@ -0,0 +1,10 @@
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
+ MULT18X18D _TECHMAP_REPLACE_ (
+ .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
+ .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
+ .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
+ .SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
+
+ .P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
+ );
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 9f409ca51..8e243f7a6 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -89,6 +89,9 @@ struct SynthEcp5Pass : public ScriptPass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
+ log(" -dsp\n");
+ log(" map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -96,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
+ bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
void clear_flags() YS_OVERRIDE
{
@@ -114,6 +117,7 @@ struct SynthEcp5Pass : public ScriptPass
abc2 = false;
vpr = false;
abc9 = false;
+ dsp = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -192,6 +196,10 @@ struct SynthEcp5Pass : public ScriptPass
abc9 = true;
continue;
}
+ if (args[argidx] == "-dsp") {
+ dsp = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -228,7 +236,28 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("coarse"))
{
- run("synth -run coarse");
+ run("opt_expr");
+ run("opt_clean");
+ run("check");
+ run("opt");
+ run("wreduce");
+ run("peepopt");
+ run("opt_clean");
+ run("share");
+ run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+ run("opt_expr");
+ run("opt_clean");
+ if (dsp) {
+ run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
+ run("clean");
+ run("techmap -map +/ecp5/dsp_map.v");
+ }
+ run("alumacc");
+ run("opt");
+ run("fsm");
+ run("opt -fast");
+ run("memory -nomap");
+ run("opt_clean");
}
if (!nobram && check_label("bram", "(skip if -nobram)"))
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 2eb9fa2c1..6ebca0d54 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -365,3 +365,44 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule
`endif
+
+module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
+ wire [47:0] P_48;
+ DSP48E1 #(
+ // Disable all registers
+ .ACASCREG(0),
+ .ADREG(0),
+ .A_INPUT("DIRECT"),
+ .ALUMODEREG(0),
+ .AREG(0),
+ .BCASCREG(0),
+ .B_INPUT("DIRECT"),
+ .BREG(0),
+ .CARRYINREG(0),
+ .CARRYINSELREG(0),
+ .CREG(0),
+ .DREG(0),
+ .INMODEREG(0),
+ .MREG(0),
+ .OPMODEREG(0),
+ .PREG(0)
+ ) _TECHMAP_REPLACE_ (
+ //Data path
+ .A({5'b0, A}),
+ .B(B),
+ .C(48'b0),
+ .D(24'b0),
+ .P(P_48),
+
+ .INMODE(4'b0000),
+ .ALUMODE(4'b0000),
+ .OPMODE(7'b000101),
+ .CARRYINSEL(3'b000),
+
+ .ACIN(30'b0),
+ .BCIN(18'b0),
+ .PCIN(48'b0),
+ .CARRYIN(1'b0)
+ );
+ assign OUT = P_48;
+endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b672a0d4f..01e75b50e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -78,6 +78,9 @@ struct SynthXilinxPass : public ScriptPass
log(" -nowidelut\n");
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
log("\n");
+ log(" -nodsp\n");
+ log(" do not use DSP48E1s to implement multipliers and associated logic\n");
+ log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
@@ -104,7 +107,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
- bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+ bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, nodsp, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@@ -122,6 +125,7 @@ struct SynthXilinxPass : public ScriptPass
nosrl = false;
nocarry = false;
nowidelut = false;
+ nodsp = false;
abc9 = false;
widemux = 0;
}
@@ -202,6 +206,10 @@ struct SynthXilinxPass : public ScriptPass
abc9 = true;
continue;
}
+ if (args[argidx] == "-nodsp") {
+ nodsp = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -249,8 +257,8 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("coarse")) {
run("proc");
- if (help_mode || flatten)
- run("flatten", "(if -flatten)");
+ if (flatten || help_mode)
+ run("flatten", "(with '-flatten')");
run("opt_expr");
run("opt_clean");
run("check");
@@ -275,6 +283,10 @@ struct SynthXilinxPass : public ScriptPass
}
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+
+ if (!nodsp || help_mode)
+ run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
+
run("alumacc");
run("share");
run("opt");
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 07:22:54 +0000