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-rw-r--r--techlibs/ecp5/cells_map.v15
-rw-r--r--techlibs/ecp5/synth_ecp5.cc22
-rw-r--r--techlibs/ice40/synth_ice40.cc5
-rw-r--r--techlibs/xilinx/Makefile.inc1
-rw-r--r--techlibs/xilinx/cells_map.v27
-rw-r--r--techlibs/xilinx/cells_sim.v236
-rw-r--r--techlibs/xilinx/cells_xtra.py28
-rw-r--r--techlibs/xilinx/cells_xtra.v160
-rw-r--r--techlibs/xilinx/synth_xilinx.cc21
-rw-r--r--techlibs/xilinx/xc6s_ff_map.v130
-rw-r--r--techlibs/xilinx/xc7_ff_map.v94
-rw-r--r--techlibs/xilinx/xilinx_dffopt.cc365
12 files changed, 884 insertions, 220 deletions
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 71ae9237b..10e89a3e0 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .
module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+`ifdef ASYNC_PRLD
+module \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule
+module \$_DLATCH_P_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(E), .DI(1'b0), .M(D), .Q(Q)); endmodule
+
+module \$_DFFSR_NNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_NNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+module \$_DFFSR_NPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_NPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+
+module \$_DFFSR_PNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_PNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+module \$_DFFSR_PPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_PPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+`endif
+
`include "cells_ff.vh"
`include "cells_io.vh"
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4cbb56ea1..16ff9c57a 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -79,6 +79,9 @@ struct SynthEcp5Pass : public ScriptPass
log(" -nowidelut\n");
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
log("\n");
+ log(" -asyncprld\n");
+ log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n");
+ log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
@@ -99,7 +102,7 @@ struct SynthEcp5Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr;
+ bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr;
void clear_flags() YS_OVERRIDE
{
@@ -112,6 +115,7 @@ struct SynthEcp5Pass : public ScriptPass
nobram = false;
nolutram = false;
nowidelut = false;
+ asyncprld = false;
flatten = true;
retime = false;
abc2 = false;
@@ -176,6 +180,10 @@ struct SynthEcp5Pass : public ScriptPass
nobram = true;
continue;
}
+ if (args[argidx] == "-asyncprld") {
+ asyncprld = true;
+ continue;
+ }
if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
nolutram = true;
continue;
@@ -292,7 +300,7 @@ struct SynthEcp5Pass : public ScriptPass
run("opt_clean");
if (!nodffe)
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
- run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
+ run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
run("opt_expr -undriven -mux_undef");
run("simplemap");
run("ecp5_ffinit");
@@ -306,12 +314,18 @@ struct SynthEcp5Pass : public ScriptPass
if (abc2 || help_mode) {
run("abc", " (only if -abc2)");
}
- std::string techmap_args = "-map +/ecp5/latches_map.v";
+ std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
if (abc9)
techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
- run("techmap " + techmap_args);
+ if (!asyncprld || abc9)
+ run("techmap " + techmap_args);
if (abc9) {
+ run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+ run("wbflip @abc9_boxes");
+ run("techmap -autoproc @abc9_boxes");
+ run("aigmap @abc9_boxes");
+ run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/ecp5/abc9_model.v");
if (nowidelut)
run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index ed7a16c08..5073ba917 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
+ run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+ run("wbflip @abc9_boxes");
+ run("techmap -autoproc @abc9_boxes");
+ run("aigmap @abc9_boxes");
+ run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 3ebc72fe8..3f2fbcc85 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -1,5 +1,6 @@
OBJS += techlibs/xilinx/synth_xilinx.o
+OBJS += techlibs/xilinx/xilinx_dffopt.o
GENFILES += techlibs/xilinx/brams_init_36.vh
GENFILES += techlibs/xilinx/brams_init_32.vh
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index de2068bc5..cc180f2b9 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -28,6 +28,33 @@ module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPL
(* techmap_celltype = "$_DFF_PN1_" *)
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$__DFFE_NN0" *)
+module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$__DFFE_PN0" *)
+module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$__DFFE_NN1" *)
+module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$__DFFE_PN1" *)
+module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+
+(* techmap_celltype = "$__DFFS_NN0_" *)
+module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$__DFFS_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$__DFFS_PN0_" *)
+module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$__DFFS_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$__DFFS_NN1_" *)
+module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$__DFFS_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$__DFFS_PN1_" *)
+module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$__DFFS_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+
+(* techmap_celltype = "$__DFFSE_NN0" *)
+module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFSE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$__DFFSE_PN0" *)
+module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFSE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$__DFFSE_NN1" *)
+module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFSE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$__DFFSE_PN1" *)
+module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFSE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;
parameter [DEPTH-1:0] INIT = 0;
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index f9ce496ff..47ba794bf 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -227,6 +227,14 @@ module MUXCY(output O, input CI, DI, S);
assign O = S ? CI : DI;
endmodule
+module MUXF5(output O, input I0, I1, S);
+ assign O = S ? I1 : I0;
+endmodule
+
+module MUXF6(output O, input I0, I1, S);
+ assign O = S ? I1 : I0;
+endmodule
+
(* abc9_box_id = 1, lib_whitebox *)
module MUXF7(output O, input I0, I1, S);
assign O = S ? I1 : I0;
@@ -237,6 +245,10 @@ module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
+module MUXF9(output O, input I0, I1, S);
+ assign O = S ? I1 : I0;
+endmodule
+
module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
@@ -258,6 +270,26 @@ module CARRY4(
assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule
+module CARRY8(
+ output [7:0] CO,
+ output [7:0] O,
+ input CI,
+ input CI_TOP,
+ input [7:0] DI, S
+);
+ parameter CARRY_TYPE = "SINGLE_CY8";
+ wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]);
+ assign O = S ^ {CO[6:4], CI4, CO[2:0], CI};
+ assign CO[0] = S[0] ? CI : DI[0];
+ assign CO[1] = S[1] ? CO[0] : DI[1];
+ assign CO[2] = S[2] ? CO[1] : DI[2];
+ assign CO[3] = S[3] ? CO[2] : DI[3];
+ assign CO[4] = S[4] ? CI4 : DI[4];
+ assign CO[5] = S[5] ? CO[4] : DI[5];
+ assign CO[6] = S[6] ? CO[5] : DI[6];
+ assign CO[7] = S[7] ? CO[6] : DI[7];
+endmodule
+
`ifdef _EXPLICIT_CARRY
module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
@@ -281,6 +313,16 @@ endmodule
`endif
+module ORCY (output O, input CI, I);
+ assign O = CI | I;
+endmodule
+
+module MULT_AND (output LO, input I0, I1);
+ assign LO = I0 & I1;
+endmodule
+
+// Flip-flops and latches.
+
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
module FDRE (
@@ -329,6 +371,41 @@ module FDSE (
endcase endgenerate
endmodule
+module FDRSE (
+ output reg Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_R_INVERTED" *)
+ input R,
+ (* invertible_pin = "IS_S_INVERTED" *)
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
+ initial Q <= INIT;
+ wire c = C ^ IS_C_INVERTED;
+ wire ce = CE ^ IS_CE_INVERTED;
+ wire d = D ^ IS_D_INVERTED;
+ wire r = R ^ IS_R_INVERTED;
+ wire s = S ^ IS_S_INVERTED;
+ always @(posedge c)
+ if (r)
+ Q <= 0;
+ else if (s)
+ Q <= 1;
+ else if (ce)
+ Q <= d;
+endmodule
+
module FDCE (
(* abc9_arrival=303 *)
output reg Q,
@@ -379,6 +456,51 @@ module FDPE (
endcase endgenerate
endmodule
+module FDCPE (
+ output wire Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input CE,
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR,
+ input D,
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ wire c = C ^ IS_C_INVERTED;
+ wire clr = CLR ^ IS_CLR_INVERTED;
+ wire pre = PRE ^ IS_PRE_INVERTED;
+ // Hacky model to avoid simulation-synthesis mismatches.
+ reg qc, qp, qs;
+ initial qc = INIT;
+ initial qp = INIT;
+ initial qs = 0;
+ always @(posedge c, posedge clr) begin
+ if (clr)
+ qc <= 0;
+ else if (CE)
+ qc <= D;
+ end
+ always @(posedge c, posedge pre) begin
+ if (pre)
+ qp <= 1;
+ else if (CE)
+ qp <= D;
+ end
+ always @* begin
+ if (clr)
+ qs <= 0;
+ else if (pre)
+ qs <= 1;
+ end
+ assign Q = qs ? qp : qc;
+endmodule
+
module FDRE_1 (
(* abc9_arrival=303 *)
output reg Q,
@@ -445,8 +567,8 @@ module LDCE (
wire clr = CLR ^ IS_CLR_INVERTED;
wire g = G ^ IS_G_INVERTED;
always @*
- if (clr) Q = 1'b0;
- else if (GE && g) Q = D;
+ if (clr) Q <= 1'b0;
+ else if (GE && g) Q <= D;
endmodule
module LDPE (
@@ -467,8 +589,59 @@ module LDPE (
wire g = G ^ IS_G_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
always @*
- if (pre) Q = 1'b1;
- else if (GE && g) Q = D;
+ if (pre) Q <= 1'b1;
+ else if (GE && g) Q <= D;
+endmodule
+
+module LDCPE (
+ output reg Q,
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G,
+ (* invertible_pin = "IS_GE_INVERTED" *)
+ input GE,
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE
+);
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter [0:0] IS_GE_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ initial Q = INIT;
+ wire d = D ^ IS_D_INVERTED;
+ wire g = G ^ IS_G_INVERTED;
+ wire ge = GE ^ IS_GE_INVERTED;
+ wire clr = CLR ^ IS_CLR_INVERTED;
+ wire pre = PRE ^ IS_PRE_INVERTED;
+ always @*
+ if (clr) Q <= 1'b0;
+ else if (pre) Q <= 1'b1;
+ else if (ge && g) Q <= d;
+endmodule
+
+module AND2B1L (
+ output O,
+ input DI,
+ (* invertible_pin = "IS_SRI_INVERTED" *)
+ input SRI
+);
+ parameter [0:0] IS_SRI_INVERTED = 1'b0;
+ assign O = DI & ~(SRI ^ IS_SRI_INVERTED);
+endmodule
+
+module OR2L (
+ output O,
+ input DI,
+ (* invertible_pin = "IS_SRI_INVERTED" *)
+ input SRI
+);
+ parameter [0:0] IS_SRI_INVERTED = 1'b0;
+ assign O = DI | (SRI ^ IS_SRI_INVERTED);
endmodule
// LUTRAM.
@@ -1334,6 +1507,20 @@ endmodule
// Shift registers.
+module SRL16 (
+ output Q,
+ input A0, A1, A2, A3,
+ (* clkbuf_sink *)
+ input CLK,
+ input D
+);
+ parameter [15:0] INIT = 16'h0000;
+
+ reg [15:0] r = INIT;
+ assign Q = r[{A3,A2,A1,A0}];
+ always @(posedge CLK) r <= { r[14:0], D };
+endmodule
+
module SRL16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc9_arrival=1472 *)
@@ -1358,6 +1545,22 @@ module SRL16E (
endgenerate
endmodule
+module SRLC16 (
+ output Q,
+ output Q15,
+ input A0, A1, A2, A3,
+ (* clkbuf_sink *)
+ input CLK,
+ input D
+);
+ parameter [15:0] INIT = 16'h0000;
+
+ reg [15:0] r = INIT;
+ assign Q15 = r[15];
+ assign Q = r[{A3,A2,A1,A0}];
+ always @(posedge CLK) r <= { r[14:0], D };
+endmodule
+
module SRLC16E (
output Q,
output Q15,
@@ -1410,6 +1613,31 @@ module SRLC32E (
endgenerate
endmodule
+module CFGLUT5 (
+ output CDO,
+ output O5,
+ output O6,
+ input I4,
+ input I3,
+ input I2,
+ input I1,
+ input I0,
+ input CDI,
+ input CE,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ wire clk = CLK ^ IS_CLK_INVERTED;
+ reg [31:0] r = INIT;
+ assign CDO = r[31];
+ assign O5 = r[{1'b0, I3, I2, I1, I0}];
+ assign O6 = r[{I4, I3, I2, I1, I0}];
+ always @(posedge clk) if (CE) r <= {r[30:0], CDI};
+endmodule
+
// DSP
// Virtex 2, Virtex 2 Pro, Spartan 3.
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index e4c580b9d..d5c58c5d7 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -65,9 +65,9 @@ CELLS = [
# CLB -- registers/latches.
# Virtex 1/2/4/5, Spartan 3.
- Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
- Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
- Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
+ # Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
+ # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
+ # Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
# Virtex 6, Spartan 6, Series 7, Ultrascale.
# Cell('FDCE'),
# Cell('FDPE'),
@@ -75,8 +75,8 @@ CELLS = [
# Cell('FDSE'),
# Cell('LDCE'),
# Cell('LDPE'),
- Cell('AND2B1L'),
- Cell('OR2L'),
+ # Cell('AND2B1L'),
+ # Cell('OR2L'),
# CLB -- other.
# Cell('LUT1'),
@@ -86,23 +86,23 @@ CELLS = [
# Cell('LUT5'),
# Cell('LUT6'),
# Cell('LUT6_2'),
- Cell('MUXF5'),
- Cell('MUXF6'),
+ # Cell('MUXF5'),
+ # Cell('MUXF6'),
# Cell('MUXF7'),
# Cell('MUXF8'),
- Cell('MUXF9'),
+ # Cell('MUXF9'),
# Cell('CARRY4'),
- Cell('CARRY8'),
+ # Cell('CARRY8'),
# Cell('MUXCY'),
# Cell('XORCY'),
- Cell('ORCY'),
- Cell('MULT_AND'),
- Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('ORCY'),
+ # Cell('MULT_AND'),
+ # Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}),
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
- Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}),
# Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}),
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
- Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
# Block RAM.
# Virtex.
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 8ac596459..c3e5c72f9 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,165 +1,5 @@
// Created by cells_xtra.py from Xilinx models
-module FDCPE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- output Q;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
- input C;
- input CE;
- (* invertible_pin = "IS_CLR_INVERTED" *)
- input CLR;
- input D;
- (* invertible_pin = "IS_PRE_INVERTED" *)
- input PRE;
-endmodule
-
-module FDRSE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_CE_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_R_INVERTED = 1'b0;
- parameter [0:0] IS_S_INVERTED = 1'b0;
- output Q;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
- input C;
- (* invertible_pin = "IS_CE_INVERTED" *)
- input CE;
- (* invertible_pin = "IS_D_INVERTED" *)
- input D;
- (* invertible_pin = "IS_R_INVERTED" *)
- input R;
- (* invertible_pin = "IS_S_INVERTED" *)
- input S;
-endmodule
-
-module LDCPE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_G_INVERTED = 1'b0;
- parameter [0:0] IS_GE_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- output Q;
- (* invertible_pin = "IS_CLR_INVERTED" *)
- input CLR;
- (* invertible_pin = "IS_D_INVERTED" *)
- input D;
- (* invertible_pin = "IS_G_INVERTED" *)
- input G;
- (* invertible_pin = "IS_GE_INVERTED" *)
- input GE;
- (* invertible_pin = "IS_PRE_INVERTED" *)
- input PRE;
-endmodule
-
-module AND2B1L (...);
- parameter [0:0] IS_SRI_INVERTED = 1'b0;
- output O;
- input DI;
- (* invertible_pin = "IS_SRI_INVERTED" *)
- input SRI;
-endmodule
-
-module OR2L (...);
- parameter [0:0] IS_SRI_INVERTED = 1'b0;
- output O;
- input DI;
- (* invertible_pin = "IS_SRI_INVERTED" *)
- input SRI;
-endmodule
-
-module MUXF5 (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module MUXF6 (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module MUXF9 (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module CARRY8 (...);
- parameter CARRY_TYPE = "SINGLE_CY8";
- output [7:0] CO;
- output [7:0] O;
- input CI;
- input CI_TOP;
- input [7:0] DI;
- input [7:0] S;
-endmodule
-
-module ORCY (...);
- output O;
- input CI;
- input I;
-endmodule
-
-module MULT_AND (...);
- output LO;
- input I0;
- input I1;
-endmodule
-
-module SRL16 (...);
- parameter [15:0] INIT = 16'h0000;
- output Q;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- input CLK;
- input D;
-endmodule
-
-module SRLC16 (...);
- parameter [15:0] INIT = 16'h0000;
- output Q;
- output Q15;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- input CLK;
- input D;
-endmodule
-
-module CFGLUT5 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- output CDO;
- output O5;
- output O6;
- input I4;
- input I3;
- input I2;
- input I1;
- input I0;
- input CDI;
- input CE;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_CLK_INVERTED" *)
- input CLK;
-endmodule
-
module RAMB16_S1 (...);
parameter [0:0] INIT = 1'h0;
parameter [0:0] SRVAL = 1'h0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2c5686a35..ff530b819 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -444,6 +444,16 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_ffram")) {
+ // Required for dffsr2dff to work.
+ run("simplemap t:$dff t:$adff t:$mux");
+ // Needs to be done before opt -mux_bool happens.
+ run("dffsr2dff");
+ if (help_mode)
+ run("dff2dffs [-match-init]", "(-match-init for xc6s only)");
+ else if (family == "xc6s")
+ run("dff2dffs -match-init");
+ else
+ run("dff2dffs");
if (widemux > 0)
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently
@@ -453,14 +463,11 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("fine")) {
- run("dffsr2dff");
- run("dff2dffe");
+ run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
if (help_mode) {
- run("simplemap t:$mux", " ('-widemux' only)");
run("muxcover <internal options>, ('-widemux' only)");
}
else if (widemux > 0) {
- run("simplemap t:$mux");
constexpr int cost_mux2 = 100;
std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
switch (widemux) {
@@ -533,6 +540,11 @@ struct SynthXilinxPass : public ScriptPass
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+ run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+ run("wbflip @abc9_boxes");
+ run("techmap -autoproc @abc9_boxes");
+ run("aigmap @abc9_boxes");
+ run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
@@ -563,6 +575,7 @@ struct SynthXilinxPass : public ScriptPass
else
techmap_args += " -map " + ff_map_file;
run("techmap " + techmap_args);
+ run("xilinx_dffopt");
run("clean");
}
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v
index bf35b09e5..c40f446e0 100644
--- a/techlibs/xilinx/xc6s_ff_map.v
+++ b/techlibs/xilinx/xc6s_ff_map.v
@@ -27,6 +27,8 @@
`ifndef _NO_FFS
+// No reset.
+
module \$_DFF_N_ (input D, C, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
@@ -46,6 +48,8 @@ module \$_DFF_P_ (input D, C, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
+// No reset, enable.
+
module \$_DFFE_NP_ (input D, C, E, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
@@ -65,80 +69,168 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q);
+// Async reset.
+
+module \$_DFF_NP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
else
- FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NP0_ (input D, C, R, output Q);
+module \$_DFF_PP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
else
- FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q);
+
+module \$_DFF_NP1_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ else
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module \$_DFF_PP1_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ else
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// Async reset, enable.
+
+module \$__DFFE_NP0 (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
else
- FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q);
+module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
else
- FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q);
+module \$__DFFE_NP1 (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
else
- FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q);
+module \$__DFFE_PP1 (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
else
- FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// Sync reset.
+
+module \$__DFFS_NP0_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with reset initialized to 1");
+ else
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q);
+module \$__DFFS_PP0_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with reset initialized to 1");
+ else
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module \$__DFFS_NP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
- $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ $error("Spartan 6 doesn't support FFs with set initialized to 0");
else
- FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+ FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q);
+module \$__DFFS_PP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
- $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ $error("Spartan 6 doesn't support FFs with set initialized to 0");
else
- FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
+// Sync reset, enable.
+
+module \$__DFFSE_NP0 (input D, C, E, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with reset initialized to 1");
+ else
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module \$__DFFSE_PP0 (input D, C, E, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with reset initialized to 1");
+ else
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module \$__DFFSE_NP1 (input D, C, E, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with set initialized to 0");
+ else
+ FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module \$__DFFSE_PP1 (input D, C, E, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with set initialized to 0");
+ else
+ FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// Latches (no reset).
+
module \$_DLATCH_N_ (input E, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
@@ -158,5 +250,7 @@ module \$_DLATCH_P_ (input E, D, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
+// Latches with reset (TODO).
+
`endif
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
index 32ca9f560..2bd874457 100644
--- a/techlibs/xilinx/xc7_ff_map.v
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -37,6 +37,8 @@
`ifndef _NO_FFS
+// No reset.
+
module \$_DFF_N_ (input D, C, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
@@ -48,6 +50,8 @@ module \$_DFF_P_ (input D, C, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
+// No reset, enable.
+
module \$_DFFE_NP_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
@@ -59,47 +63,103 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q);
+// Async reset.
+
+module \$_DFF_NP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NP0_ (input D, C, R, output Q);
+module \$_DFF_PP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q);
+
+module \$_DFF_NP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q);
+module \$_DFF_PP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q);
+// Async reset, enable.
+
+module \$__DFFE_NP0 (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q);
+module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q);
+
+module \$__DFFE_NP1 (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q);
+module \$__DFFE_PP1 (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
- FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// Sync reset.
+
+module \$__DFFS_NP0_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
+module \$__DFFS_PP0_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module \$__DFFS_NP1_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module \$__DFFS_PP1_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// Sync reset, enable.
+
+module \$__DFFSE_NP0 (input D, C, E, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module \$__DFFSE_PP0 (input D, C, E, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module \$__DFFSE_NP1 (input D, C, E, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+module \$__DFFSE_PP1 (input D, C, E, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// Latches (no reset).
module \$_DLATCH_N_ (input E, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
@@ -112,5 +172,7 @@ module \$_DLATCH_P_ (input E, D, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
+// Latches with reset (TODO).
+
`endif
diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
new file mode 100644
index 000000000..13a0b9b83
--- /dev/null
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -0,0 +1,365 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+typedef std::pair<Const, std::vector<SigBit>> LutData;
+
+// Compute a LUT implementing (select ^ select_inv) ? alt_data : data. Returns true if successful.
+bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) {
+ // First, gather input signals -- insert new signals at the beginning
+ // of the vector, so they don't disturb the likely-critical D LUT input
+ // timings.
+ result.second = data.second;
+ // D lut inputs initially start at 0.
+ int idx_data = 0;
+ // Now add the control input LUT inputs.
+ std::vector<int> idx_sel;
+ for (auto bit : select.second) {
+ int idx = -1;
+ for (int i = 0; i < GetSize(result.second); i++)
+ if (result.second[i] == bit)
+ idx = i;
+ if (idx == -1) {
+ idx = 0;
+ // Insert new signal at the beginning and bump all indices.
+ result.second.insert(result.second.begin(), bit);
+ idx_data++;
+ for (int &sidx : idx_sel)
+ sidx++;
+ }
+ idx_sel.push_back(idx);
+ }
+ // Insert the Q signal, if any, to the slowest input -- it will have
+ // no problem meeting timing.
+ int idx_alt = -1;
+ if (alt_data.wire) {
+ // Check if we already have it.
+ for (int i = 0; i < GetSize(result.second); i++)
+ if (result.second[i] == alt_data)
+ idx_alt = i;
+ // If not, add it.
+ if (idx_alt == -1) {
+ idx_alt = 0;
+ result.second.insert(result.second.begin(), alt_data);
+ idx_data++;
+ for (int &sidx : idx_sel)
+ sidx++;
+ }
+ }
+
+ // If LUT would be too large, bail.
+ if (GetSize(result.second) > max_lut_size)
+ return false;
+
+ // Okay, we're doing it — compute the LUT mask.
+ result.first = Const(0, 1 << GetSize(result.second));
+ for (int i = 0; i < GetSize(result.first); i++) {
+ int sel_lut_idx = 0;
+ for (int j = 0; j < GetSize(select.second); j++)
+ if (i & 1 << idx_sel[j])
+ sel_lut_idx |= 1 << j;
+ bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
+ bool new_bit;
+ if (select_val ^ select_inv) {
+ // Use alt_data.
+ if (alt_data.wire)
+ new_bit = (i & 1 << idx_alt) != 0;
+ else
+ new_bit = alt_data.data == State::S1;
+ } else {
+ // Use original LUT.
+ int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
+ new_bit = data.first.bits[lut_idx] == State::S1;
+ }
+ result.first.bits[i] = new_bit ? State::S1 : State::S0;
+ }
+ return true;
+}
+
+struct XilinxDffOptPass : public Pass {
+ XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" xilinx_dffopt [options] [selection]\n");
+ log("\n");
+ log("Converts hardware clock enable and set/reset signals on FFs to emulation\n");
+ log("using LUTs, if doing so would improve area. Operates on post-techmap Xilinx\n");
+ log("cells (LUT*, FD*).\n");
+ log("\n");
+ log(" -lut4\n");
+ log(" Assume a LUT4-based device (instead of a LUT6-based device).\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n");
+
+ size_t argidx;
+ int max_lut_size = 6;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-lut4") {
+ max_lut_size = 4;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ {
+ log("Optimizing FFs in %s.\n", log_id(module));
+
+ SigMap sigmap(module);
+ dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
+ dict<SigBit, int> bit_uses;
+
+ // Gather LUTs.
+ for (auto cell : module->selected_cells())
+ {
+ for (auto port : cell->connections())
+ for (auto bit : port.second)
+ bit_uses[sigmap(bit)]++;
+ if (cell->get_bool_attribute(ID::keep))
+ continue;
+ if (cell->type == ID(INV)) {
+ SigBit sigout = sigmap(cell->getPort(ID(O)));
+ SigBit sigin = sigmap(cell->getPort(ID(I)));
+ bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell);
+ } else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) {
+ SigBit sigout = sigmap(cell->getPort(ID(O)));
+ const Const &init = cell->getParam(ID(INIT));
+ std::vector<SigBit> sigin;
+ sigin.push_back(sigmap(cell->getPort(ID(I0))));
+ if (cell->type == ID(LUT1))
+ goto lut_sigin_done;
+ sigin.push_back(sigmap(cell->getPort(ID(I1))));
+ if (cell->type == ID(LUT2))
+ goto lut_sigin_done;
+ sigin.push_back(sigmap(cell->getPort(ID(I2))));
+ if (cell->type == ID(LUT3))
+ goto lut_sigin_done;
+ sigin.push_back(sigmap(cell->getPort(ID(I3))));
+ if (cell->type == ID(LUT4))
+ goto lut_sigin_done;
+ sigin.push_back(sigmap(cell->getPort(ID(I4))));
+ if (cell->type == ID(LUT5))
+ goto lut_sigin_done;
+ sigin.push_back(sigmap(cell->getPort(ID(I5))));
+lut_sigin_done:
+ bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
+ }
+ }
+ for (auto wire : module->wires())
+ if (wire->port_output || wire->port_input)
+ for (int i = 0; i < GetSize(wire); i++)
+ bit_uses[sigmap(SigBit(wire, i))]++;
+
+ // Iterate through FFs.
+ for (auto cell : module->selected_cells())
+ {
+ bool has_s = false, has_r = false;
+ if (cell->type.in(ID(FDCE), ID(FDPE), ID(FDCPE), ID(FDCE_1), ID(FDPE_1), ID(FDCPE_1))) {
+ // Async reset.
+ } else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
+ has_r = true;
+ } else if (cell->type.in(ID(FDSE), ID(FDSE_1))) {
+ has_s = true;
+ } else if (cell->type.in(ID(FDRSE), ID(FDRSE_1))) {
+ has_r = true;
+ has_s = true;
+ } else {
+ // Not a FF.
+ continue;
+ }
+ if (cell->get_bool_attribute(ID::keep))
+ continue;
+
+ // Don't bother if D has more than one use.
+ SigBit sig_D = sigmap(cell->getPort(ID(D)));
+ if (bit_uses[sig_D] > 2)
+ continue;
+
+ // Find the D LUT.
+ auto it_D = bit_to_lut.find(sig_D);
+ if (it_D == bit_to_lut.end())
+ continue;
+ LutData lut_d = it_D->second.first;
+ Cell *cell_d = it_D->second.second;
+ if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
+ // Flip all bits in the LUT.
+ for (int i = 0; i < GetSize(lut_d.first); i++)
+ lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
+ }
+
+ LutData lut_d_post_ce;
+ LutData lut_d_post_s;
+ LutData lut_d_post_r;
+ bool worthy_post_ce = false;
+ bool worthy_post_s = false;
+ bool worthy_post_r = false;
+
+ // First, unmap CE.
+ SigBit sig_Q = sigmap(cell->getPort(ID(Q)));
+ SigBit sig_CE = sigmap(cell->getPort(ID(CE)));
+ LutData lut_ce = LutData(Const(2, 2), {sig_CE});
+ auto it_CE = bit_to_lut.find(sig_CE);
+ if (it_CE != bit_to_lut.end())
+ lut_ce = it_CE->second.first;
+ if (sig_CE.wire) {
+ // Merge CE LUT and D LUT into one. If it cannot be done, nothing to do about this FF.
+ if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size))
+ continue;
+
+ // If this gets rid of a CE LUT, it's worth it. If not, it still may be worth it, if we can remove set/reset as well.
+ if (it_CE != bit_to_lut.end())
+ worthy_post_ce = true;
+ } else if (sig_CE.data != State::S1) {
+ // Strange. Should not happen in a reasonable flow, so bail.
+ continue;
+ } else {
+ lut_d_post_ce = lut_d;
+ }
+
+ // Second, unmap S, if any.
+ lut_d_post_s = lut_d_post_ce;
+ if (has_s) {
+ SigBit sig_S = sigmap(cell->getPort(ID(S)));
+ LutData lut_s = LutData(Const(2, 2), {sig_S});
+ bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
+ auto it_S = bit_to_lut.find(sig_S);
+ if (it_S != bit_to_lut.end())
+ lut_s = it_S->second.first;
+ if (sig_S.wire) {
+ // Merge S LUT and D LUT into one. If it cannot be done, try to at least merge CE.
+ if (!merge_lut(lut_d_post_s, lut_d_post_ce, lut_s, inv_s, SigBit(State::S1), max_lut_size))
+ goto unmap;
+ // If this gets rid of an S LUT, it's worth it.
+ if (it_S != bit_to_lut.end())
+ worthy_post_s = true;
+ } else if (sig_S.data != (inv_s ? State::S1 : State::S0)) {
+ // Strange. Should not happen in a reasonable flow, so bail.
+ continue;
+ }
+ }
+
+ // Third, unmap R, if any.
+ lut_d_post_r = lut_d_post_s;
+ if (has_r) {
+ SigBit sig_R = sigmap(cell->getPort(ID(R)));
+ LutData lut_r = LutData(Const(2, 2), {sig_R});
+ bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
+ auto it_R = bit_to_lut.find(sig_R);
+ if (it_R != bit_to_lut.end())
+ lut_r = it_R->second.first;
+ if (sig_R.wire) {
+ // Merge R LUT and D LUT into one. If it cannot be done, try to at least merge CE/S.
+ if (!merge_lut(lut_d_post_r, lut_d_post_s, lut_r, inv_r, SigBit(State::S0), max_lut_size))
+ goto unmap;
+ // If this gets rid of an S LUT, it's worth it.
+ if (it_R != bit_to_lut.end())
+ worthy_post_r = true;
+ } else if (sig_R.data != (inv_r ? State::S1 : State::S0)) {
+ // Strange. Should not happen in a reasonable flow, so bail.
+ continue;
+ }
+ }
+
+unmap:
+ LutData final_lut;
+ if (worthy_post_r) {
+ final_lut = lut_d_post_r;
+ log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+ } else if (worthy_post_s) {
+ final_lut = lut_d_post_s;
+ log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+ } else if (worthy_post_ce) {
+ final_lut = lut_d_post_ce;
+ log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+ } else {
+ // Nothing to do here.
+ continue;
+ }
+
+ // Okay, we're doing it. Unmap ports.
+ if (worthy_post_r) {
+ cell->unsetParam(ID(IS_R_INVERTED));
+ cell->setPort(ID(R), Const(0, 1));
+ }
+ if (has_s && (worthy_post_r || worthy_post_s)) {
+ cell->unsetParam(ID(IS_S_INVERTED));
+ cell->setPort(ID(S), Const(0, 1));
+ }
+ cell->setPort(ID(CE), Const(1, 1));
+ cell->unsetParam(ID(IS_D_INVERTED));
+
+ // Create the new LUT.
+ Cell *lut_cell = 0;
+ switch (GetSize(final_lut.second)) {
+ case 1:
+ lut_cell = module->addCell(NEW_ID, ID(LUT1));
+ break;
+ case 2:
+ lut_cell = module->addCell(NEW_ID, ID(LUT2));
+ break;
+ case 3:
+ lut_cell = module->addCell(NEW_ID, ID(LUT3));
+ break;
+ case 4:
+ lut_cell = module->addCell(NEW_ID, ID(LUT4));
+ break;
+ case 5:
+ lut_cell = module->addCell(NEW_ID, ID(LUT5));
+ break;
+ case 6:
+ lut_cell = module->addCell(NEW_ID, ID(LUT6));
+ break;
+ default:
+ log_assert(!"unknown lut size");
+ }
+ lut_cell->attributes = cell_d->attributes;
+ Wire *lut_out = module->addWire(NEW_ID);
+ lut_cell->setParam(ID(INIT), final_lut.first);
+ cell->setPort(ID(D), lut_out);
+ lut_cell->setPort(ID(O), lut_out);
+ lut_cell->setPort(ID(I0), final_lut.second[0]);
+ if (GetSize(final_lut.second) >= 2)
+ lut_cell->setPort(ID(I1), final_lut.second[1]);
+ if (GetSize(final_lut.second) >= 3)
+ lut_cell->setPort(ID(I2), final_lut.second[2]);
+ if (GetSize(final_lut.second) >= 4)
+ lut_cell->setPort(ID(I3), final_lut.second[3]);
+ if (GetSize(final_lut.second) >= 5)
+ lut_cell->setPort(ID(I4), final_lut.second[4]);
+ if (GetSize(final_lut.second) >= 6)
+ lut_cell->setPort(ID(I5), final_lut.second[5]);
+ }
+ }
+ }
+} XilinxDffOptPass;
+
+PRIVATE_NAMESPACE_END
+
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 00:51:31 +0000