diff options
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/anlogic/anlogic_determine_init.cc | 4 | ||||
| -rw-r--r-- | techlibs/anlogic/anlogic_eqn.cc | 4 | ||||
| -rw-r--r-- | techlibs/gowin/determine_init.cc | 4 | ||||
| -rw-r--r-- | techlibs/xilinx/xc6s_brams_map.v | 6 |
4 files changed, 9 insertions, 9 deletions
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc index 34b1d4f8a..c4089dac2 100644 --- a/techlibs/anlogic/anlogic_determine_init.cc +++ b/techlibs/anlogic/anlogic_determine_init.cc @@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass { } } } - log_header(design, "Updated %lu cells with determined init value.\n", cnt); + log_header(design, "Updated %d cells with determined init value.\n", cnt); } } AnlogicDetermineInitPass; diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index 741bf04cc..070d39a20 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass { } } } - log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt); + log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt); } } AnlogicEqnPass; diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc index 991e5245a..d9a0880f6 100644 --- a/techlibs/gowin/determine_init.cc +++ b/techlibs/gowin/determine_init.cc @@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass { } } } - log_header(design, "Updated %lu cells with determined init value.\n", cnt); + log_header(design, "Updated %d cells with determined init value.\n", cnt); } } DetermineInitPass; diff --git a/techlibs/xilinx/xc6s_brams_map.v b/techlibs/xilinx/xc6s_brams_map.v index c9b33af42..16fd15e74 100644 --- a/techlibs/xilinx/xc6s_brams_map.v +++ b/techlibs/xilinx/xc6s_brams_map.v @@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK2 ^ !CLKPOL2), .ENBRDEN(A1EN), .REGCEBREGCE(|1), - .RSTB(|0) + .RSTBRST(|0) ); endmodule @@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end else begin @@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end endgenerate |