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-rw-r--r--techlibs/common/simlib.v44
-rw-r--r--techlibs/common/synth.cc2
-rw-r--r--techlibs/coolrunner2/coolrunner2_sop.cc22
-rw-r--r--techlibs/ecp5/cells_sim.v22
-rw-r--r--techlibs/ice40/cells_map.v2
-rw-r--r--techlibs/ice40/cells_sim.v10
-rw-r--r--techlibs/ice40/ice40_braminit.cc6
-rw-r--r--techlibs/ice40/ice40_opt.cc2
-rw-r--r--techlibs/ice40/synth_ice40.cc2
-rw-r--r--techlibs/intel/Makefile.inc20
-rw-r--r--techlibs/xilinx/Makefile.inc4
-rw-r--r--techlibs/xilinx/cells_sim.v28
-rw-r--r--techlibs/xilinx/lutrams.txt (renamed from techlibs/xilinx/drams.txt)0
-rw-r--r--techlibs/xilinx/lutrams_map.v (renamed from techlibs/xilinx/drams_map.v)0
-rw-r--r--techlibs/xilinx/synth_xilinx.cc33
15 files changed, 117 insertions, 80 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a424d3089..7845a3fed 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,14 +532,26 @@ endmodule
// --------------------------------------------------------
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $lcu (P, G, CI, CO)
+//-
+//- Lookahead carry unit
+//- A building block dedicated to fast computation of carry-bits used in binary
+//- arithmetic operations. By replacing the ripple carry structure used in full-adder
+//- blocks, the more significant bits of the sum can be expected to be computed more
+//- quickly.
+//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
+//- +/techmap.v).
module \$lcu (P, G, CI, CO);
parameter WIDTH = 1;
-input [WIDTH-1:0] P, G;
-input CI;
+input [WIDTH-1:0] P; // Propagate
+input [WIDTH-1:0] G; // Generate
+input CI; // Carry-in
-output reg [WIDTH-1:0] CO;
+output reg [WIDTH-1:0] CO; // Carry-out
integer i;
always @* begin
@@ -555,6 +567,17 @@ endmodule
// --------------------------------------------------------
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $alu (A, B, CI, BI, X, Y, CO)
+//-
+//- Arithmetic logic unit.
+//- A building block supporting both binary addition/subtraction operations, and
+//- indirectly, comparison operations.
+//- Typically created by the `alumacc` pass, which transforms:
+//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+//- cells into this $alu cell.
+//-
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
@@ -563,12 +586,16 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] X, Y;
+input [A_WIDTH-1:0] A; // Input operand
+input [B_WIDTH-1:0] B; // Input operand
+output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,
+ // used in combination with
+ // reduction-AND for $eq/$ne ops)
+output [Y_WIDTH-1:0] Y; // Sum
-input CI, BI;
-output [Y_WIDTH-1:0] CO;
+input CI; // Carry-in (set for $sub)
+input BI; // Invert-B (set for $sub)
+output [Y_WIDTH-1:0] CO; // Carry-out
wire [Y_WIDTH-1:0] AA, BB;
@@ -584,6 +611,7 @@ endgenerate
wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
assign X = AA ^ BB;
+// Full adder
assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
function get_carry;
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 555de9fba..a176357a7 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass
log_cmd_error("This command only operates on fully selected designs!\n");
if (abc == "abc9" && !lut)
- log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
+ log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
log_header(design, "Executing SYNTH pass.\n");
log_push();
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 48da0d8ad..de0cbb29d 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
- cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
- cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
- cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
+ if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
+ "\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
{
if (cell->hasPort("\\PRE"))
special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
@@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
pool<SigBit> sig_fed_by_ff;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
- cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
- cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
- cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+ if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+ "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
{
auto output = sigmap(cell->getPort("\\Q")[0]);
sig_fed_by_ff.insert(output);
@@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
// Look at all the FF inputs
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
- cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
- cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
- cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+ if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+ "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
{
SigBit input;
- if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+ if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(cell->getPort("\\T")[0]);
else
input = sigmap(cell->getPort("\\D")[0]);
@@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", xor_to_ff_wire);
- if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+ if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire);
else
cell->setPort("\\D", xor_to_ff_wire);
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 3d343b315..2fcb0369e 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
endmodule
// ---------------------------------------
-(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
-module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
- output S0, S1, COUT);
-
+(* abc_box_id=1, lib_whitebox *)
+module CCU2C(
+ (* abc_carry *) input CIN,
+ input A0, B0, C0, D0, A1, B1, C1, D1,
+ output S0, S1,
+ (* abc_carry *) output COUT
+);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES";
@@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
-//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
+//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
- input [3:0] DI,
- input [3:0] WAD,
- input WRE, WCK,
- input [3:0] RAD,
+ (* abc_scc_break *) input [3:0] DI,
+ (* abc_scc_break *) input [3:0] WAD,
+ (* abc_scc_break *) input WRE,
+ input WCK,
+ input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0c10c9ac4..662423f0a 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
.WIDTH(4),
.LUT(LUT)
) lut (
- .A({I3,B,A,I0}),
+ .A({I0,A,B,I3}),
.Y(O)
);
endmodule
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2205be27d..ab04808f4 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+(* abc_box_id = 1, lib_whitebox *)
+module \$__ICE40_FULL_ADDER (
+ (* abc_carry *) output CO,
+ output O,
+ input A,
+ input B,
+ (* abc_carry *) input CI
+);
SB_CARRY carry (
.I0(A),
.I1(B),
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 4fa6b0792..1a139ffea 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
for (int i = 0; i < GetSize(line); i++)
{
- if (in_comment && line.substr(i, 2) == "*/") {
+ if (in_comment && line.compare(i, 2, "*/") == 0) {
line[i] = ' ';
line[i+1] = ' ';
in_comment = false;
continue;
}
- if (!in_comment && line.substr(i, 2) == "/*")
+ if (!in_comment && line.compare(i, 2, "/*") == 0)
in_comment = true;
if (in_comment)
line[i] = ' ';
@@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
long value;
token = next_token(line, " \t\r\n");
- if (token.empty() || token.substr(0, 2) == "//")
+ if (token.empty() || token.compare(0, 2, "//") == 0)
break;
if (token[0] == '@') {
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index e492454fb..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
- cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+ cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8f4a0f377..c6de81bd9 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -183,7 +183,7 @@ struct SynthIce40Pass : public ScriptPass
continue;
}
if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
- min_ce_use = std::stoi(args[++argidx]);
+ min_ce_use = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-nobram") {
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index 7a3d2c71a..4e8f423c8 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -5,20 +5,10 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
-$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
-$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
-$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
-$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
-$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
-$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v))
-$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
-$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
-#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))
-#$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/arith_map.v))
-#$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/arith_map.v))
+
+# Add the cell models and mappings for the VQM backend
+families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive
+$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
+$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 2c6e7432e..2b1af289c 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -32,8 +32,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 05e46b4e7..bec9ea1a0 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -181,8 +181,14 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
-(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
-module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
+(* abc_box_id = 4, lib_whitebox *)
+module CARRY4(
+ (* abc_carry *) output [3:0] CO,
+ output [3:0] O,
+ (* abc_carry *) input CI,
+ input CYINIT,
+ input [3:0] DI, S
+);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
@@ -289,10 +295,12 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
-(* abc_box_id = 5, abc_scc_break="D,WE" *)
+(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
- input D, WCLK, WE,
+ (* abc_scc_break *) input D,
+ input WCLK,
+ (* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@@ -307,10 +315,12 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
-(* abc_box_id = 6, abc_scc_break="D,WE" *)
+(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
- input D, WCLK, WE,
+ (* abc_scc_break *) input D,
+ input WCLK,
+ (* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@@ -325,10 +335,12 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
-(* abc_box_id = 7, abc_scc_break="D,WE" *)
+(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
- input D, WCLK, WE,
+ (* abc_scc_break *) input D,
+ input WCLK,
+ (* abc_scc_break *) input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/lutrams.txt
index 2613c206c..2613c206c 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/lutrams.txt
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/lutrams_map.v
index 77041ca86..77041ca86 100644
--- a/techlibs/xilinx/drams_map.v
+++ b/techlibs/xilinx/lutrams_map.v
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b672a0d4f..7ba67409b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -64,13 +64,13 @@ struct SynthXilinxPass : public ScriptPass
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -nobram\n");
- log(" disable inference of block rams\n");
+ log(" do not use block RAM cells in output netlist\n");
log("\n");
- log(" -nodram\n");
- log(" disable inference of distributed rams\n");
+ log(" -nolutram\n");
+ log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -nosrl\n");
- log(" disable inference of shift registers\n");
+ log(" do not use distributed SRL cells in output netlist\n");
log("\n");
log(" -nocarry\n");
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
@@ -104,7 +104,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
- bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+ bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@@ -118,7 +118,7 @@ struct SynthXilinxPass : public ScriptPass
vpr = false;
nocarry = false;
nobram = false;
- nodram = false;
+ nolutram = false;
nosrl = false;
nocarry = false;
nowidelut = false;
@@ -186,8 +186,8 @@ struct SynthXilinxPass : public ScriptPass
nobram = true;
continue;
}
- if (args[argidx] == "-nodram") {
- nodram = true;
+ if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+ nolutram = true;
continue;
}
if (args[argidx] == "-nosrl") {
@@ -195,7 +195,7 @@ struct SynthXilinxPass : public ScriptPass
continue;
}
if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
- widemux = std::stoi(args[++argidx]);
+ widemux = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-abc9") {
@@ -284,7 +284,7 @@ struct SynthXilinxPass : public ScriptPass
run("opt_clean");
}
- if (check_label("bram", "(skip if '-nobram')")) {
+ if (check_label("map_bram", "(skip if '-nobram')")) {
if (help_mode) {
run("memory_bram -rules +/xilinx/{family}_brams.txt");
run("techmap -map +/xilinx/{family}_brams_map.v");
@@ -301,20 +301,23 @@ struct SynthXilinxPass : public ScriptPass
}
}
- if (check_label("dram", "(skip if '-nodram')")) {
- if (!nodram || help_mode) {
- run("memory_bram -rules +/xilinx/drams.txt");
- run("techmap -map +/xilinx/drams_map.v");
+ if (check_label("map_lutram", "(skip if '-nolutram')")) {
+ if (!nolutram || help_mode) {
+ run("memory_bram -rules +/xilinx/lutrams.txt");
+ run("techmap -map +/xilinx/lutrams_map.v");
}
}
- if (check_label("fine")) {
+ if (check_label("map_ffram")) {
if (widemux > 0)
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently
else
run("opt -fast -full");
run("memory_map");
+ }
+
+ if (check_label("fine")) {
run("dffsr2dff");
run("dff2dffe");
if (help_mode) {
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 20:04:14 +0000