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-rw-r--r--techlibs/common/adff2dff.v2
-rw-r--r--techlibs/common/cmp2lcu.v29
-rw-r--r--techlibs/common/cmp2lut.v14
-rw-r--r--techlibs/common/mul2dsp.v48
-rw-r--r--techlibs/common/simlib.v10
-rw-r--r--techlibs/ice40/brams_map.v73
-rw-r--r--techlibs/machxo2/Makefile.inc5
-rw-r--r--techlibs/machxo2/cells_map.v34
-rw-r--r--techlibs/machxo2/cells_sim.v212
-rw-r--r--techlibs/machxo2/synth_machxo2.cc248
-rw-r--r--techlibs/nexus/cells_sim.v115
-rw-r--r--techlibs/xilinx/arith_map.v6
-rw-r--r--techlibs/xilinx/cells_sim.v80
-rw-r--r--techlibs/xilinx/xilinx_dffopt.cc6
14 files changed, 792 insertions, 90 deletions
diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v
index eca0110eb..2e4357b64 100644
--- a/techlibs/common/adff2dff.v
+++ b/techlibs/common/adff2dff.v
@@ -11,7 +11,7 @@ module adff2dff (CLK, ARST, D, Q);
(* force_downto *)
output reg [WIDTH-1:0] Q;
(* force_downto *)
- wire reg [WIDTH-1:0] NEXT_Q;
+ reg [WIDTH-1:0] NEXT_Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index a221727e7..4e62039e9 100644
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -41,10 +41,7 @@ generate
wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
// For $ge operation, start with the assumption that A and B are
// equal (propagating this equality if A and B turn out to be so)
- if (_TECHMAP_CELLTYPE_ == "$ge")
- localparam CI = 1'b1;
- else
- localparam CI = 1'b0;
+ localparam CI = _TECHMAP_CELLTYPE_ == "$ge";
$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
end
@@ -81,12 +78,12 @@ generate
assign Y = CO[LCU_WIDTH-1];
end
else begin
- if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
- localparam COST = 0;
- else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
- localparam COST = 1;
- else
- localparam COST = 2;
+ localparam COST =
+ _TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
+ ? 0
+ : (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
+ ? 1
+ : 2);
if (BUDGET < COST)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
@@ -104,21 +101,21 @@ generate
// from MSB down, deferring to less significant bits if the
// MSBs are equal
assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
+ (* force_downto *)
+ wire [LCU_WIDTH-1:0] P_, G_;
if (LCU_WIDTH == 1) begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
- wire P_ = P[0] & PP;
+ assign P_ = P[0] & PP;
// Generate if any comparisons call for it
- wire G_ = G[0] | GG;
+ assign G_ = G[0] | GG;
end
else begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
- (* force_downto *)
- wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
+ assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
// Generate if any comparisons call for it
- (* force_downto *)
- wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
+ assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
end
if (AB_WIDTH == 1)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
index ec8f98e8d..c753bd2f1 100644
--- a/techlibs/common/cmp2lut.v
+++ b/techlibs/common/cmp2lut.v
@@ -66,14 +66,12 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
endfunction
generate
- if (_TECHMAP_CELLTYPE_ == "$lt")
- localparam operation = 0;
- if (_TECHMAP_CELLTYPE_ == "$le")
- localparam operation = 1;
- if (_TECHMAP_CELLTYPE_ == "$gt")
- localparam operation = 2;
- if (_TECHMAP_CELLTYPE_ == "$ge")
- localparam operation = 3;
+ localparam operation =
+ _TECHMAP_CELLTYPE_ == "$lt" ? 0 :
+ _TECHMAP_CELLTYPE_ == "$le" ? 1 :
+ _TECHMAP_CELLTYPE_ == "$gt" ? 2 :
+ _TECHMAP_CELLTYPE_ == "$ge" ? 3 :
+ -1;
if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
wire _TECHMAP_FAIL_ = 1;
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index bec47d01f..f22f47b4a 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -121,7 +121,7 @@ module _80_mul (A, B, Y);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
- if (A_SIGNED && B_SIGNED) begin
+ if (A_SIGNED && B_SIGNED) begin : blk
(* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -129,7 +129,7 @@ module _80_mul (A, B, Y);
(* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end
- else begin
+ else begin : blk
(* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -148,15 +148,15 @@ module _80_mul (A, B, Y);
) mul (
.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
.B(B),
- .Y(partial[i])
+ .Y(blk.partial[i])
);
// TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary
// reduction' approach also exists...
if (i == 0)
- assign partial_sum[i] = partial[i];
+ assign blk.partial_sum[i] = blk.partial[i];
else
- assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
+ assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
end
\$__mul #(
@@ -168,17 +168,17 @@ module _80_mul (A, B, Y);
) sliceA.last (
.A(A[A_WIDTH-1 -: last_A_WIDTH]),
.B(B),
- .Y(last_partial)
+ .Y(blk.last_partial)
);
- assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
- assign Y = partial_sum[n];
+ assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
+ assign Y = blk.partial_sum[n];
end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
- if (A_SIGNED && B_SIGNED) begin
+ if (A_SIGNED && B_SIGNED) begin : blk
(* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -186,7 +186,7 @@ module _80_mul (A, B, Y);
(* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end
- else begin
+ else begin : blk
(* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -205,15 +205,15 @@ module _80_mul (A, B, Y);
) mul (
.A(A),
.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
- .Y(partial[i])
+ .Y(blk.partial[i])
);
// TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary
// reduction' approach also exists...
if (i == 0)
- assign partial_sum[i] = partial[i];
+ assign blk.partial_sum[i] = blk.partial[i];
else
- assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
+ assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
end
\$__mul #(
@@ -225,20 +225,24 @@ module _80_mul (A, B, Y);
) mul_sliceB_last (
.A(A),
.B(B[B_WIDTH-1 -: last_B_WIDTH]),
- .Y(last_partial)
+ .Y(blk.last_partial)
);
- assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
- assign Y = partial_sum[n];
+ assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
+ assign Y = blk.partial_sum[n];
end
else begin
- if (A_SIGNED)
+ if (A_SIGNED) begin : blkA
wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
- else
+ end
+ else begin : blkA
wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
- if (B_SIGNED)
+ end
+ if (B_SIGNED) begin : blkB
wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
- else
+ end
+ else begin : blkB
wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
+ end
`DSP_NAME #(
.A_SIGNED(A_SIGNED),
@@ -247,8 +251,8 @@ module _80_mul (A, B, Y);
.B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
) _TECHMAP_REPLACE_ (
- .A(Aext),
- .B(Bext),
+ .A(blkA.Aext),
+ .B(blkB.Bext),
.Y(Y)
);
end
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e94884025..5c9efad27 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -237,7 +237,7 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
-//- $reduce_and (A, B, Y)
+//- $reduce_and (A, Y)
//-
//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.
//-
@@ -264,7 +264,7 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
-//- $reduce_or (A, B, Y)
+//- $reduce_or (A, Y)
//-
//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.
//-
@@ -291,7 +291,7 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
-//- $reduce_xor (A, B, Y)
+//- $reduce_xor (A, Y)
//-
//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.
//-
@@ -318,7 +318,7 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
-//- $reduce_xnor (A, B, Y)
+//- $reduce_xnor (A, Y)
//-
//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.
//-
@@ -345,7 +345,7 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
-//- $reduce_bool (A, B, Y)
+//- $reduce_bool (A, Y)
//-
//- An OR reduction. This cell type is used instead of $reduce_or when a signal is
//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index ad3bccd21..db9f5d8ce 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -254,6 +254,41 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B
wire [15:0] A1DATA_16, B1DATA_16;
+`define INSTANCE \
+ \$__ICE40_RAM4K #( \
+ .READ_MODE(MODE), \
+ .WRITE_MODE(MODE), \
+ .NEGCLK_R(!CLKPOL2), \
+ .NEGCLK_W(!CLKPOL3), \
+ .INIT_0(INIT_0), \
+ .INIT_1(INIT_1), \
+ .INIT_2(INIT_2), \
+ .INIT_3(INIT_3), \
+ .INIT_4(INIT_4), \
+ .INIT_5(INIT_5), \
+ .INIT_6(INIT_6), \
+ .INIT_7(INIT_7), \
+ .INIT_8(INIT_8), \
+ .INIT_9(INIT_9), \
+ .INIT_A(INIT_A), \
+ .INIT_B(INIT_B), \
+ .INIT_C(INIT_C), \
+ .INIT_D(INIT_D), \
+ .INIT_E(INIT_E), \
+ .INIT_F(INIT_F) \
+ ) _TECHMAP_REPLACE_ ( \
+ .RDATA(A1DATA_16), \
+ .RADDR(A1ADDR_11), \
+ .RCLK(CLK2), \
+ .RCLKE(A1EN), \
+ .RE(1'b1), \
+ .WDATA(B1DATA_16), \
+ .WADDR(B1ADDR_11), \
+ .WCLK(CLK3), \
+ .WCLKE(|B1EN), \
+ .WE(1'b1) \
+ );
+
generate
if (MODE == 1) begin
assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
@@ -261,51 +296,23 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B
assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
`include "brams_init1.vh"
+ `INSTANCE
end
if (MODE == 2) begin
assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
`include "brams_init2.vh"
+ `INSTANCE
end
if (MODE == 3) begin
assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
`include "brams_init3.vh"
+ `INSTANCE
end
endgenerate
- \$__ICE40_RAM4K #(
- .READ_MODE(MODE),
- .WRITE_MODE(MODE),
- .NEGCLK_R(!CLKPOL2),
- .NEGCLK_W(!CLKPOL3),
- .INIT_0(INIT_0),
- .INIT_1(INIT_1),
- .INIT_2(INIT_2),
- .INIT_3(INIT_3),
- .INIT_4(INIT_4),
- .INIT_5(INIT_5),
- .INIT_6(INIT_6),
- .INIT_7(INIT_7),
- .INIT_8(INIT_8),
- .INIT_9(INIT_9),
- .INIT_A(INIT_A),
- .INIT_B(INIT_B),
- .INIT_C(INIT_C),
- .INIT_D(INIT_D),
- .INIT_E(INIT_E),
- .INIT_F(INIT_F)
- ) _TECHMAP_REPLACE_ (
- .RDATA(A1DATA_16),
- .RADDR(A1ADDR_11),
- .RCLK(CLK2),
- .RCLKE(A1EN),
- .RE(1'b1),
- .WDATA(B1DATA_16),
- .WADDR(B1ADDR_11),
- .WCLK(CLK3),
- .WCLKE(|B1EN),
- .WE(1'b1)
- );
+`undef INSTANCE
+
endmodule
diff --git a/techlibs/machxo2/Makefile.inc b/techlibs/machxo2/Makefile.inc
new file mode 100644
index 000000000..6f6f6ce94
--- /dev/null
+++ b/techlibs/machxo2/Makefile.inc
@@ -0,0 +1,5 @@
+
+OBJS += techlibs/machxo2/synth_machxo2.o
+
+$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v))
+$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v))
diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v
new file mode 100644
index 000000000..82eb10d95
--- /dev/null
+++ b/techlibs/machxo2/cells_map.v
@@ -0,0 +1,34 @@
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+ input [WIDTH-1:0] A;
+ output Y;
+
+ localparam rep = 1<<(4-WIDTH);
+ wire [3:0] I;
+
+ generate
+ if(WIDTH == 1) begin
+ assign I = {1'b0, 1'b0, 1'b0, A[0]};
+ end else if(WIDTH == 2) begin
+ assign I = {1'b0, 1'b0, A[1], A[0]};
+ end else if(WIDTH == 3) begin
+ assign I = {1'b0, A[2], A[1], A[0]};
+ end else if(WIDTH == 4) begin
+ assign I = {A[3], A[2], A[1], A[0]};
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
+
+ LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
+endmodule
+
+// DFFs
+module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+// IO- "$__" cells for the iopadmap pass.
+module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule
+module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule
+module \$__FACADE_TOUTPAD (input I, OE, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(~OE)); endmodule
+module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(~OE)); endmodule
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
new file mode 100644
index 000000000..161ddfe2e
--- /dev/null
+++ b/techlibs/machxo2/cells_sim.v
@@ -0,0 +1,212 @@
+module LUT4 #(
+ parameter [15:0] INIT = 0
+) (
+ input A, B, C, D,
+ output Z
+);
+ // This form of LUT propagates as few x's as possible.
+ wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
+ wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
+ assign Z = A ? s1[1] : s1[0];
+endmodule
+
+module FACADE_FF #(
+ parameter GSR = "ENABLED",
+ parameter CEMUX = "1",
+ parameter CLKMUX = "0",
+ parameter LSRMUX = "LSR",
+ parameter LSRONMUX = "LSRMUX",
+ parameter SRMODE = "LSR_OVER_CE",
+ parameter REGSET = "SET",
+ parameter REGMODE = "FF"
+) (
+ input CLK, DI, LSR, CE,
+ output reg Q
+);
+
+ wire muxce;
+ generate
+ case (CEMUX)
+ "1": assign muxce = 1'b1;
+ "0": assign muxce = 1'b0;
+ "INV": assign muxce = ~CE;
+ default: assign muxce = CE;
+ endcase
+ endgenerate
+
+ wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+ wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
+ wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+ wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+
+ initial Q = srval;
+
+ generate
+ if (REGMODE == "FF") begin
+ if (SRMODE == "ASYNC") begin
+ always @(posedge muxclk, posedge muxlsron)
+ if (muxlsron)
+ Q <= srval;
+ else if (muxce)
+ Q <= DI;
+ end else begin
+ always @(posedge muxclk)
+ if (muxlsron)
+ Q <= srval;
+ else if (muxce)
+ Q <= DI;
+ end
+ end else if (REGMODE == "LATCH") begin
+ ERROR_UNSUPPORTED_FF_MODE error();
+ end else begin
+ ERROR_UNKNOWN_FF_MODE error();
+ end
+ endgenerate
+endmodule
+
+/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
+module PFUMX (input ALUT, BLUT, C0, output Z);
+ assign Z = C0 ? ALUT : BLUT;
+endmodule
+
+/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
+module L6MUX21 (input D0, D1, SD, output Z);
+ assign Z = SD ? D1 : D0;
+endmodule
+
+/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
+prjtrellis were filled in clockwise order from bottom left. */
+module FACADE_SLICE #(
+ parameter MODE = "LOGIC",
+ parameter GSR = "ENABLED",
+ parameter SRMODE = "LSR_OVER_CE",
+ parameter CEMUX = "1",
+ parameter CLKMUX = "0",
+ parameter LSRMUX = "LSR",
+ parameter LSRONMUX = "LSRMUX",
+ parameter LUT0_INITVAL = 16'hFFFF,
+ parameter LUT1_INITVAL = 16'hFFFF,
+ parameter REGMODE = "FF",
+ parameter REG0_SD = "1",
+ parameter REG1_SD = "1",
+ parameter REG0_REGSET = "SET",
+ parameter REG1_REGSET = "SET",
+ parameter CCU2_INJECT1_0 = "YES",
+ parameter CCU2_INJECT1_1 = "YES",
+ parameter WREMUX = "INV"
+) (
+ input A0, B0, C0, D0,
+ input A1, B1, C1, D1,
+ input M0, M1,
+ input FCI, FXA, FXB,
+
+ input CLK, LSR, CE,
+ input DI0, DI1,
+
+ input WD0, WD1,
+ input WAD0, WAD1, WAD2, WAD3,
+ input WRE, WCK,
+
+ output F0, Q0,
+ output F1, Q1,
+ output FCO, OFX0, OFX1,
+
+ output WDO0, WDO1, WDO2, WDO3,
+ output WADO0, WADO1, WADO2, WADO3
+);
+
+ generate
+ if (MODE == "LOGIC") begin
+ L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
+
+ wire k0;
+ wire k1;
+ PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0));
+
+ LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0));
+ LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1));
+
+ assign F0 = k0;
+ assign F1 = k1;
+ end else if (MODE == "CCU2") begin
+ ERROR_UNSUPPORTED_SLICE_MODE error();
+ end else if (MODE == "DPRAM") begin
+ ERROR_UNSUPPORTED_SLICE_MODE error();
+ end else begin
+ ERROR_UNKNOWN_SLICE_MODE error();
+ end
+ endgenerate
+
+ /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
+ outputs (in other words, feeds back into FACADE_SLICE). */
+ wire di0 = (REG0_SD == "1") ? DI0 : M0;
+ wire di1 = (REG1_SD == "1") ? DI1 : M1;
+
+ FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
+ .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
+ .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
+ FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
+ .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
+ .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
+endmodule
+
+module FACADE_IO #(
+ parameter DIR = "INPUT"
+) (
+ inout PAD,
+ input I, T,
+ output O
+);
+ generate
+ if (DIR == "INPUT") begin
+ assign O = PAD;
+ end else if (DIR == "OUTPUT") begin
+ assign PAD = T ? 1'bz : I;
+ end else if (DIR == "BIDIR") begin
+ assign PAD = T ? 1'bz : I;
+ assign O = PAD;
+ end else begin
+ ERROR_UNKNOWN_IO_MODE error();
+ end
+ endgenerate
+endmodule
+
+(* blackbox *)
+module OSCH #(
+ parameter NOM_FREQ = "2.08"
+) (
+ input STDBY,
+ output OSC,
+ output SEDSTDBY
+);
+endmodule
+
+(* blackbox *)
+module DCCA (
+ input CLKI,
+ input CE,
+ output CLKO
+);
+endmodule
+
+(* blackbox *)
+module DCMA (
+ input CLK0,
+ input CLK1,
+ input SEL,
+ output DCMOUT
+);
+endmodule
+
+// IO- "$__" cells for the iopadmap pass. These are temporary cells not meant
+// to be instantiated by the end user. They are required in this file for
+// attrmvcp to work.
+(* blackbox *)
+module \$__FACADE_OUTPAD (input I, output O); endmodule
+(* blackbox *)
+module \$__FACADE_INPAD (input I, output O); endmodule
+(* blackbox *)
+module \$__FACADE_TOUTPAD (input I, OE, output O); endmodule
+(* blackbox *)
+module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); endmodule
diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc
new file mode 100644
index 000000000..bd56fbba9
--- /dev/null
+++ b/techlibs/machxo2/synth_machxo2.cc
@@ -0,0 +1,248 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 William D. Jones <wjones@wdj-consulting.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthMachXO2Pass : public ScriptPass
+{
+ SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { }
+
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_machxo2 [options]\n");
+ log("\n");
+ log("This command runs synthesis for MachXO2 FPGAs.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module\n");
+ log("\n");
+ log(" -blif <file>\n");
+ log(" write the design to the specified BLIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -edif <file>\n");
+ log(" write the design to the specified EDIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -noiopad\n");
+ log(" do not insert IO buffers\n");
+ log("\n");
+ log(" -vpr\n");
+ log(" generate an output netlist (and BLIF file) suitable for VPR\n");
+ log(" (this feature is experimental and incomplete)\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_opt, blif_file, edif_file, json_file;
+ bool flatten, vpr, noiopad;
+
+ void clear_flags() override
+ {
+ top_opt = "-auto-top";
+ blif_file = "";
+ edif_file = "";
+ json_file = "";
+ flatten = true;
+ vpr = false;
+ noiopad = false;
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+ blif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+ edif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
+ if (args[argidx] == "-flatten") {
+ flatten = true;
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-noiopad") {
+ noiopad = true;
+ continue;
+ }
+ if (args[argidx] == "-vpr") {
+ vpr = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This command only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_MACHXO2 pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ void script() override
+ {
+ if (check_label("begin"))
+ {
+ run("read_verilog -lib -icells +/machxo2/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ }
+
+ if (check_label("flatten", "(unless -noflatten)"))
+ {
+ if (flatten || help_mode) {
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
+ }
+
+ if (check_label("coarse"))
+ {
+ run("synth -run coarse");
+ }
+
+ if (check_label("fine"))
+ {
+ run("memory_map");
+ run("opt -full");
+ run("techmap -map +/techmap.v");
+ run("opt -fast");
+ }
+
+ if (check_label("map_ios", "(unless -noiopad)"))
+ {
+ if (!noiopad || help_mode)
+ {
+ run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD OE:I:O -tinoutpad $__FACADE_TINOUTPAD OE:O:I:B A:top");
+ run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]");
+ run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]");
+ }
+ }
+
+ if (check_label("map_ffs"))
+ {
+ run("dfflegalize -cell $_DFF_P_ 0");
+ }
+
+ if (check_label("map_luts"))
+ {
+ run("abc -lut 4 -dress");
+ run("clean");
+ }
+
+ if (check_label("map_cells"))
+ {
+ run("techmap -map +/machxo2/cells_map.v");
+ run("clean");
+ }
+
+ if (check_label("check"))
+ {
+ run("hierarchy -check");
+ run("stat");
+ }
+
+ if (check_label("blif"))
+ {
+ if (!blif_file.empty() || help_mode) {
+ if (vpr || help_mode) {
+ run(stringf("opt_clean -purge"),
+ " (vpr mode)");
+ run(stringf("write_blif -attr -cname -conn -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()),
+ " (vpr mode)");
+ }
+ if (!vpr)
+ run(stringf("write_blif -gates -attr -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()),
+ " (non-vpr mode)");
+ }
+ }
+
+ if (check_label("edif"))
+ {
+ if (!edif_file.empty() || help_mode)
+ run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+ }
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+ }
+ }
+} SynthMachXO2Pass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/nexus/cells_sim.v b/techlibs/nexus/cells_sim.v
index b5938e08f..1e876a210 100644
--- a/techlibs/nexus/cells_sim.v
+++ b/techlibs/nexus/cells_sim.v
@@ -941,3 +941,118 @@ module MULTADDSUB36X36 #(
.Z(Z)
);
endmodule
+
+module MULTADDSUB9X9WIDE #(
+ parameter REGINPUTAB0 = "REGISTER",
+ parameter REGINPUTAB1 = "REGISTER",
+ parameter REGINPUTAB2 = "REGISTER",
+ parameter REGINPUTAB3 = "REGISTER",
+ parameter REGINPUTC = "REGISTER",
+ parameter REGADDSUB = "REGISTER",
+ parameter REGLOADC = "REGISTER",
+ parameter REGLOADC2 = "REGISTER",
+ parameter REGPIPELINE = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [8:0] A0, B0, A1, B1, A2, B2, A3, B3,
+ input [53:0] C,
+ input CLK,
+ input CEA0A1, CEA2A3,
+ input RSTA0A1, RSTA2A3,
+ input CEB0B1, CEB2B3,
+ input RSTB0B1, RSTB2B3,
+ input CEC, RSTC,
+ input CECTRL, RSTCTRL,
+ input SIGNED,
+ input RSTPIPE, CEPIPE,
+ input RSTOUT, CEOUT,
+ input LOADC,
+ input [3:0] ADDSUB,
+ output [53:0] Z
+);
+ wire [17:0] m0, m1, m2, m3;
+
+ localparam M_WIDTH = 18;
+ localparam Z_WIDTH = 54;
+
+ MULT9X9 #(
+ .REGINPUTA(REGINPUTAB0), .REGINPUTB(REGINPUTAB0), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
+ ) m9_0 (
+ .A(A0), .B(B0), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
+ .CLK(CLK),
+ .CEA(CEA0A1), .RSTA(RSTA0A1),
+ .CEB(CEB0B1), .RSTB(RSTB0B1),
+ .CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
+ .Z(m0)
+ );
+ MULT9X9 #(
+ .REGINPUTA(REGINPUTAB1), .REGINPUTB(REGINPUTAB1), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
+ ) m9_1 (
+ .A(A1), .B(B1), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
+ .CLK(CLK),
+ .CEA(CEA0A1), .RSTA(RSTA0A1),
+ .CEB(CEB0B1), .RSTB(RSTB0B1),
+ .CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
+ .Z(m1)
+ );
+ MULT9X9 #(
+ .REGINPUTA(REGINPUTAB2), .REGINPUTB(REGINPUTAB2), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
+ ) m9_2 (
+ .A(A2), .B(B2), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
+ .CLK(CLK),
+ .CEA(CEA2A3), .RSTA(RSTA2A3),
+ .CEB(CEB2B3), .RSTB(RSTB2B3),
+ .CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
+ .Z(m2)
+ );
+ MULT9X9 #(
+ .REGINPUTA(REGINPUTAB3), .REGINPUTB(REGINPUTAB3), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
+ ) m9_3 (
+ .A(A3), .B(B3), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
+ .CLK(CLK),
+ .CEA(CEA2A3), .RSTA(RSTA2A3),
+ .CEB(CEB2B3), .RSTB(RSTB2B3),
+ .CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
+ .Z(m3)
+ );
+
+ wire [53:0] c_r, c_r2;
+ wire [3:0] addsub_r, addsub_r2;
+ wire sgd_r, sgd_r2, csgd_r, csgd_r2;
+ wire loadc_r, loadc_r2;
+
+ OXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNED, ADDSUB}, {sgd_r, addsub_r});
+ OXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});
+
+ OXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);
+ OXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);
+
+ OXIDE_DSP_REG #(55, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNED, C}, {csgd_r, c_r});
+ OXIDE_DSP_REG #(55, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});
+
+
+ wire [18:0] m0_ext, m1_ext, m2_ext, m3_ext;
+
+ assign m0_ext = {sgd_r2 ? m0[M_WIDTH-1] : 1'b0, m0};
+ assign m1_ext = {sgd_r2 ? m1[M_WIDTH-1] : 1'b0, m1};
+ assign m2_ext = {sgd_r2 ? m2[M_WIDTH-1] : 1'b0, m2};
+ assign m3_ext = {sgd_r2 ? m3[M_WIDTH-1] : 1'b0, m3};
+
+ wire [18:0] s0 = addsub_r2[2] ? (m0_ext - m1_ext) : (m0_ext + m1_ext);
+ wire [18:0] s1 = addsub_r2[3] ? (m2_ext - m3_ext) : (m2_ext + m3_ext);
+
+ wire [53:0] s0_ext = {{(54-19){sgd_r2 ? s0[18] : 1'b0}}, s0};
+ wire [53:0] s1_ext = {{(54-19){sgd_r2 ? s1[18] : 1'b0}}, s1};
+
+ wire [53:0] c_op = loadc_r2 ? c_r2 : Z;
+
+ // The diagram in the docs is wrong! It is not two cascaded 2-input add/subs as shown,
+ // but a three-input unit with negation controls on two inputs (i.e. addsub_r2[0]
+ // negates s1 not (s1 +/- s0))
+ wire [53:0] z_d = c_op + (addsub_r2[0] ? -s1_ext : s1_ext) + (addsub_r2[1] ? -s0_ext : s0_ext);
+
+ OXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);
+
+endmodule
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index eb8a04bde..63be7563e 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -151,6 +151,8 @@ generate if (`LUT_SIZE == 4) begin
);
end endgenerate
+ assign X = S;
+
end else begin
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
@@ -193,8 +195,8 @@ end else begin
end
end endgenerate
-end endgenerate
-
assign X = S;
+
+end endgenerate
endmodule
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index adaf7aee1..a079f1c95 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -633,6 +633,41 @@ module FDRSE (
Q <= d;
endmodule
+module FDRSE_1 (
+ output reg Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_R_INVERTED" *)
+ input R,
+ (* invertible_pin = "IS_S_INVERTED" *)
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
+ initial Q <= INIT;
+ wire c = C ^ IS_C_INVERTED;
+ wire ce = CE ^ IS_CE_INVERTED;
+ wire d = D ^ IS_D_INVERTED;
+ wire r = R ^ IS_R_INVERTED;
+ wire s = S ^ IS_S_INVERTED;
+ always @(negedge c)
+ if (r)
+ Q <= 0;
+ else if (s)
+ Q <= 1;
+ else if (ce)
+ Q <= d;
+endmodule
+
(* abc9_box, lib_whitebox *)
module FDCE (
output reg Q,
@@ -837,6 +872,51 @@ module FDCPE (
assign Q = qs ? qp : qc;
endmodule
+module FDCPE_1 (
+ output wire Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input CE,
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR,
+ input D,
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ wire c = C ^ IS_C_INVERTED;
+ wire clr = CLR ^ IS_CLR_INVERTED;
+ wire pre = PRE ^ IS_PRE_INVERTED;
+ // Hacky model to avoid simulation-synthesis mismatches.
+ reg qc, qp, qs;
+ initial qc = INIT;
+ initial qp = INIT;
+ initial qs = 0;
+ always @(negedge c, posedge clr) begin
+ if (clr)
+ qc <= 0;
+ else if (CE)
+ qc <= D;
+ end
+ always @(negedge c, posedge pre) begin
+ if (pre)
+ qp <= 1;
+ else if (CE)
+ qp <= D;
+ end
+ always @* begin
+ if (clr)
+ qs <= 0;
+ else if (pre)
+ qs <= 1;
+ end
+ assign Q = qs ? qp : qc;
+endmodule
+
module LDCE (
output reg Q,
(* invertible_pin = "IS_CLR_INVERTED" *)
diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
index 365f505fb..598f1b216 100644
--- a/techlibs/xilinx/xilinx_dffopt.cc
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -209,7 +209,7 @@ lut_sigin_done:
continue;
LutData lut_d = it_D->second.first;
Cell *cell_d = it_D->second.second;
- if (cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
+ if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
// Flip all bits in the LUT.
for (int i = 0; i < GetSize(lut_d.first); i++)
lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
@@ -249,7 +249,7 @@ lut_sigin_done:
if (has_s) {
SigBit sig_S = sigmap(cell->getPort(ID::S));
LutData lut_s = LutData(Const(2, 2), {sig_S});
- bool inv_s = cell->getParam(ID(IS_S_INVERTED)).as_bool();
+ bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
auto it_S = bit_to_lut.find(sig_S);
if (it_S != bit_to_lut.end())
lut_s = it_S->second.first;
@@ -271,7 +271,7 @@ lut_sigin_done:
if (has_r) {
SigBit sig_R = sigmap(cell->getPort(ID::R));
LutData lut_r = LutData(Const(2, 2), {sig_R});
- bool inv_r = cell->getParam(ID(IS_R_INVERTED)).as_bool();
+ bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
auto it_R = bit_to_lut.find(sig_R);
if (it_R != bit_to_lut.end())
lut_r = it_R->second.first;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 22:26:07 +0000