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-rw-r--r--techlibs/common/cmp2lcu.v8
-rw-r--r--techlibs/common/techmap.v29
-rw-r--r--techlibs/ecp5/cells_bb.v4
-rw-r--r--techlibs/ice40/cells_sim.v2
-rw-r--r--techlibs/ice40/synth_ice40.cc29
5 files changed, 49 insertions, 23 deletions
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index b6f4aeed6..e42f346d1 100644
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -108,8 +108,12 @@ generate
// Generate if any comparisons call for it
wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
end
- $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
- _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
+ if (AB_WIDTH == 1)
+ $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
+ _TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));
+ else
+ $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
+ _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
end
end
endgenerate
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index ecf4d5dc5..225cff449 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -285,13 +285,32 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
output [Y_WIDTH-1:0] CO;
- wire [Y_WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- wire [Y_WIDTH-1:0] AA = A_buf;
+ wire [Y_WIDTH-1:0] AA, BB;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+ if (A_WIDTH == 0) begin
+ wire [Y_WIDTH-1:0] B_buf;
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ assign AA = {Y_WIDTH{1'b0}};
+ assign BB = BI ? ~B_buf : B_buf;
+ end
+ else if (B_WIDTH == 0) begin
+ wire [Y_WIDTH-1:0] A_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+
+ assign AA = A_buf;
+ assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}};
+ end
+ else begin
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ assign AA = A_buf;
+ assign BB = BI ? ~B_buf : B_buf;
+ end
+
\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
assign X = AA ^ BB;
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index ae124e7a3..756f05366 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -652,6 +652,10 @@ module DCUA(
parameter CH1_PROTOCOL = "8B10B";
parameter CH0_CDR_MAX_RATE = "2.5";
parameter CH1_CDR_MAX_RATE = "2.5";
+ parameter CH0_TXDEPRE = "DISABLED";
+ parameter CH1_TXDEPRE = "DISABLED";
+ parameter CH0_TXDEPOST = "DISABLED";
+ parameter CH1_TXDEPOST = "DISABLED";
endmodule
(* blackbox *)
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 6a0e3031e..5d107989d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1908,7 +1908,7 @@ module ICESTORM_LC (
o_reg <= SR_pd ? SET_NORESET : lut_o;
reg o_reg_async = 1'b0;
- always @(posedge polarized_clk, posedge SR)
+ always @(posedge polarized_clk, posedge SR_pd)
if (SR_pd)
o_reg_async <= SET_NORESET;
else if (CEN_pu)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2b211572d..6e05ab0b2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -225,10 +225,10 @@ struct SynthIce40Pass : public ScriptPass
device_opt = args[++argidx];
continue;
}
- if (args[argidx] == "-flowmap") {
- flowmap = true;
- continue;
- }
+ if (args[argidx] == "-flowmap") {
+ flowmap = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -240,13 +240,12 @@ struct SynthIce40Pass : public ScriptPass
if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
-
- if (abc9 && noabc)
- log_cmd_error("-abc9 is incompatible with -noabc!\n");
- if (abc9 && flowmap)
- log_cmd_error("-abc9 is incompatible with -flowmap!\n");
- if (flowmap && noabc)
- log_cmd_error("-flowmap is incompatible with -noabc!\n");
+ if (abc9 && noabc)
+ log_cmd_error("-abc9 is incompatible with -noabc!\n");
+ if (abc9 && flowmap)
+ log_cmd_error("-abc9 is incompatible with -flowmap!\n");
+ if (flowmap && noabc)
+ log_cmd_error("-flowmap is incompatible with -noabc!\n");
log_header(design, "Executing SYNTH_ICE40 pass.\n");
log_push();
@@ -372,10 +371,10 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)");
- if (noabc || help_mode)
- run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
- if (flowmap || help_mode)
- run("flowmap -maxlut 4", "(only if -flowmap)");
+ if (noabc || help_mode)
+ run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+ if (flowmap || help_mode)
+ run("flowmap -maxlut 4", "(only if -flowmap)");
}
if (!noabc) {
if (abc9) {