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-rw-r--r--techlibs/common/synth.cc9
-rw-r--r--techlibs/ecp5/synth_ecp5.cc20
-rw-r--r--techlibs/gowin/synth_gowin.cc20
-rw-r--r--techlibs/ice40/synth_ice40.cc22
4 files changed, 64 insertions, 7 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 79e5933e0..63395c368 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -81,6 +81,11 @@ struct SynthPass : public ScriptPass
log(" -flowmap\n");
log(" use FlowMap LUT techmapping instead of ABC\n");
log("\n");
+ log(" -no-rw-check\n");
+ log(" marks all recognized read ports as \"return don't-care value on\n");
+ log(" read/write collision\" (same result as setting the no_rw_check\n");
+ log(" attribute on all memories).\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -175,6 +180,10 @@ struct SynthPass : public ScriptPass
flowmap = true;
continue;
}
+ if (args[argidx] == "-no-rw-check") {
+ memory_opts += " -no-rw-check";
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 8c7ea5b39..f2dc534f9 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -103,6 +103,11 @@ struct SynthEcp5Pass : public ScriptPass
log(" -nodsp\n");
log(" do not map multipliers to MULT18X18D\n");
log("\n");
+ log(" -no-rw-check\n");
+ log(" marks all recognized read ports as \"return don't-care value on\n");
+ log(" read/write collision\" (same result as setting the no_rw_check\n");
+ log(" attribute on all memories).\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -110,7 +115,7 @@ struct SynthEcp5Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr;
+ bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr, no_rw_check;
void clear_flags() override
{
@@ -131,6 +136,7 @@ struct SynthEcp5Pass : public ScriptPass
vpr = false;
abc9 = false;
nodsp = false;
+ no_rw_check = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -221,6 +227,10 @@ struct SynthEcp5Pass : public ScriptPass
nodsp = true;
continue;
}
+ if (args[argidx] == "-no-rw-check") {
+ no_rw_check = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -241,6 +251,12 @@ struct SynthEcp5Pass : public ScriptPass
void script() override
{
+ std::string no_rw_check_opt = "";
+ if (no_rw_check)
+ no_rw_check_opt = " -no-rw-check";
+ if (help_mode)
+ no_rw_check_opt = " [-no-rw-check]";
+
if (check_label("begin"))
{
run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
@@ -273,7 +289,7 @@ struct SynthEcp5Pass : public ScriptPass
}
run("alumacc");
run("opt");
- run("memory -nomap");
+ run("memory -nomap" + no_rw_check_opt);
run("opt_clean");
}
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index d900bd255..15a0c41e0 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -81,6 +81,11 @@ struct SynthGowinPass : public ScriptPass
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
+ log(" -no-rw-check\n");
+ log(" marks all recognized read ports as \"return don't-care value on\n");
+ log(" read/write collision\" (same result as setting the no_rw_check\n");
+ log(" attribute on all memories).\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -88,7 +93,7 @@ struct SynthGowinPass : public ScriptPass
}
string top_opt, vout_file, json_file;
- bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu;
+ bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu, no_rw_check;
void clear_flags() override
{
@@ -104,6 +109,7 @@ struct SynthGowinPass : public ScriptPass
abc9 = false;
noiopads = false;
noalu = false;
+ no_rw_check = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -172,6 +178,10 @@ struct SynthGowinPass : public ScriptPass
noiopads = true;
continue;
}
+ if (args[argidx] == "-no-rw-check") {
+ no_rw_check = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -189,6 +199,12 @@ struct SynthGowinPass : public ScriptPass
void script() override
{
+ std::string no_rw_check_opt = "";
+ if (no_rw_check)
+ no_rw_check_opt = " -no-rw-check";
+ if (help_mode)
+ no_rw_check_opt = " [-no-rw-check]";
+
if (check_label("begin"))
{
run("read_verilog -specify -lib +/gowin/cells_sim.v");
@@ -205,7 +221,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("coarse"))
{
- run("synth -run coarse");
+ run("synth -run coarse" + no_rw_check_opt);
}
if (check_label("map_ram"))
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c10b7003e..1174f6e04 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -112,6 +112,11 @@ struct SynthIce40Pass : public ScriptPass
log(" -flowmap\n");
log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
log("\n");
+ log(" -no-rw-check\n");
+ log(" marks all recognized read ports as \"return don't-care value on\n");
+ log(" read/write collision\" (same result as setting the no_rw_check\n");
+ log(" attribute on all memories).\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -119,7 +124,7 @@ struct SynthIce40Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file, device_opt;
- bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap;
+ bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap, no_rw_check;
int min_ce_use;
void clear_flags() override
@@ -142,6 +147,7 @@ struct SynthIce40Pass : public ScriptPass
abc9 = false;
flowmap = false;
device_opt = "hx";
+ no_rw_check = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -244,6 +250,10 @@ struct SynthIce40Pass : public ScriptPass
flowmap = true;
continue;
}
+ if (args[argidx] == "-no-rw-check") {
+ no_rw_check = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -279,6 +289,12 @@ struct SynthIce40Pass : public ScriptPass
define = "-D ICE40_U";
else
define = "-D ICE40_HX";
+ std::string no_rw_check_opt = "";
+ if (no_rw_check)
+ no_rw_check_opt = " -no-rw-check";
+ if (help_mode)
+ no_rw_check_opt = " [-no-rw-check]";
+
if (check_label("begin"))
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
@@ -311,7 +327,7 @@ struct SynthIce40Pass : public ScriptPass
run("opt_expr");
run("opt_clean");
if (help_mode || dsp) {
- run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first
+ run("memory_dff" + no_rw_check_opt); // ice40_dsp will merge registers, reserve memory port registers first
run("wreduce t:$mul");
run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
@@ -326,7 +342,7 @@ struct SynthIce40Pass : public ScriptPass
}
run("alumacc");
run("opt");
- run("memory -nomap");
+ run("memory -nomap" + no_rw_check_opt);
run("opt_clean");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 00:20:26 +0000