19 files changed, 300 insertions, 201 deletions
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index b6f4aeed6..e42f346d1 100644
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -108,8 +108,12 @@ generate
                 // Generate if any comparisons call for it
                 wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
             end
-            $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
-                _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
+            if (AB_WIDTH == 1)
+               $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
+                    _TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));
+            else
+               $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
+                    _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
         end
     end
 endgenerate
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index ecf4d5dc5..225cff449 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -285,13 +285,32 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
 	input CI, BI;
 	output [Y_WIDTH-1:0] CO;
 
-	wire [Y_WIDTH-1:0] A_buf, B_buf;
-	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-	wire [Y_WIDTH-1:0] AA = A_buf;
+	wire [Y_WIDTH-1:0] AA, BB;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 
+	if (A_WIDTH == 0) begin
+		wire [Y_WIDTH-1:0] B_buf;
+		\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+		assign AA = {Y_WIDTH{1'b0}};
+		assign BB = BI ? ~B_buf : B_buf;
+	end
+	else if (B_WIDTH == 0) begin
+		wire [Y_WIDTH-1:0] A_buf;
+		\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+
+		assign AA = A_buf;
+		assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}};
+	end
+	else begin
+		wire [Y_WIDTH-1:0] A_buf, B_buf;
+		\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+		\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+		assign AA = A_buf;
+		assign BB = BI ? ~B_buf : B_buf;
+	end
+
 	\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index e4ee4991f..217151e96 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -2,6 +2,15 @@
 OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \
         techlibs/ecp5/ecp5_gsr.o
 
+GENFILES += techlibs/ecp5/bram_init_1_2_4.vh
+GENFILES += techlibs/ecp5/bram_init_9_18_36.vh
+GENFILES += techlibs/ecp5/bram_conn_1.vh
+GENFILES += techlibs/ecp5/bram_conn_2.vh
+GENFILES += techlibs/ecp5/bram_conn_4.vh
+GENFILES += techlibs/ecp5/bram_conn_9.vh
+GENFILES += techlibs/ecp5/bram_conn_18.vh
+GENFILES += techlibs/ecp5/bram_conn_36.vh
+
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index ae124e7a3..756f05366 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -652,6 +652,10 @@ module DCUA(
 	parameter CH1_PROTOCOL = "8B10B";
 	parameter CH0_CDR_MAX_RATE = "2.5";
 	parameter CH1_CDR_MAX_RATE = "2.5";
+	parameter CH0_TXDEPRE = "DISABLED";
+	parameter CH1_TXDEPRE = "DISABLED";
+	parameter CH0_TXDEPOST = "DISABLED";
+	parameter CH1_TXDEPOST = "DISABLED";
 endmodule
 
 (* blackbox *)
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index ab740ea0d..b9b236a0c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,6 +30,11 @@ struct SynthEcp5Pass : public ScriptPass
 {
 	SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
 
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
+	}
+
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -324,6 +329,14 @@ struct SynthEcp5Pass : public ScriptPass
 
 			if (abc9) {
 				run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
+				std::string abc9_opts;
+				if (nowidelut)
+					abc9_opts += " -maxlut 4";
+				std::string k = "synth_ecp5.abc9.W";
+				if (active_design && active_design->scratchpad.count(k))
+					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+				else
+					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
 				if (nowidelut)
 					run("abc9 -maxlut 4 -W 200");
 				else
diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc
index fe5d9d6e6..0756e3bcf 100644
--- a/techlibs/gowin/Makefile.inc
+++ b/techlibs/gowin/Makefile.inc
@@ -2,6 +2,7 @@
 OBJS += techlibs/gowin/synth_gowin.o
 OBJS += techlibs/gowin/determine_init.o
 
+GENFILES += techlibs/gowin/bram_init_16.vh
 
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
@@ -11,8 +12,6 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
 
-
-
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh))
 
 EXTRA_OBJS += techlibs/gowin/brams_init.mk
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 6a0e3031e..5d107989d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1908,7 +1908,7 @@ module ICESTORM_LC (
 			o_reg <= SR_pd ? SET_NORESET : lut_o;
 
 	reg o_reg_async = 1'b0;
-	always @(posedge polarized_clk, posedge SR)
+	always @(posedge polarized_clk, posedge SR_pd)
 		if (SR_pd)
 			o_reg_async <= SET_NORESET;
 		else if (CEN_pu)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9724b7dd5..6e05ab0b2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,6 +29,13 @@ struct SynthIce40Pass : public ScriptPass
 {
 	SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
 
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250";
+		RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400";
+		RTLIL::constpad["synth_ice40.abc9.u.W"] = "750";
+	}
+
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -218,10 +225,10 @@ struct SynthIce40Pass : public ScriptPass
 				device_opt = args[++argidx];
 				continue;
 			}
-            if (args[argidx] == "-flowmap") {
-                flowmap = true;
-                continue;
-            }
+			if (args[argidx] == "-flowmap") {
+				flowmap = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -233,13 +240,12 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (abc9 && retime)
 			log_cmd_error("-retime option not currently compatible with -abc9!\n");
-
-        if (abc9 && noabc)
-            log_cmd_error("-abc9 is incompatible with -noabc!\n");
-        if (abc9 && flowmap)
-            log_cmd_error("-abc9 is incompatible with -flowmap!\n");
-        if (flowmap && noabc)
-            log_cmd_error("-flowmap is incompatible with -noabc!\n");
+		if (abc9 && noabc)
+			log_cmd_error("-abc9 is incompatible with -noabc!\n");
+		if (abc9 && flowmap)
+			log_cmd_error("-abc9 is incompatible with -flowmap!\n");
+		if (flowmap && noabc)
+			log_cmd_error("-flowmap is incompatible with -noabc!\n");
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
@@ -365,22 +371,23 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/ice40/latches_map.v");
 			if (noabc || flowmap || help_mode) {
 				run("simplemap", "                               (if -noabc or -flowmap)");
-                if (noabc || help_mode)
-				    run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
-                if (flowmap || help_mode)
-                    run("flowmap -maxlut 4", "(only if -flowmap)");
+				if (noabc || help_mode)
+					run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+				if (flowmap || help_mode)
+					run("flowmap -maxlut 4", "(only if -flowmap)");
 			}
 			if (!noabc) {
 				if (abc9) {
 					run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
-					int wire_delay;
-					if (device_opt == "lp")
-						wire_delay = 400;
-					else if (device_opt == "u")
-						wire_delay = 750;
-					else
-						wire_delay = 250;
-					run(stringf("abc9 -W %d", wire_delay));
+					std::string abc9_opts;
+					std::string k = "synth_ice40.abc9.W";
+					if (active_design && active_design->scratchpad.count(k))
+						abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+					else {
+						k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
+						abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+					}
+					run("abc9 " + abc9_opts);
 				}
 				else
 					run("abc -dress -lut 4", "(skip if -noabc)");
diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index 66204c8fc..ed6c4510b 100644
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -7,17 +7,14 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/al
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
 
 # RAM
 bramtypes := m10k m20k
 $(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype).txt)))
 $(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype)_map.v)))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab_map.v))
-
-families := cyclonev cyclone10gx
 
 # Miscellaneous
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/quartus_rename.v))
-$(foreach family, $(families), $(eval $(call add_share_file,share/intel_alm/$(family),techlibs/intel_alm/$(family)/quartus_rename.v)))
diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v
index e5566010d..061463c3e 100644
--- a/techlibs/intel_alm/common/bram_m10k_map.v
+++ b/techlibs/intel_alm/common/bram_m10k_map.v
@@ -28,4 +28,4 @@ altsyncram #(
     .clock1(CLK1)
 );
 
-endmodule
+endmodule
diff --git a/techlibs/intel_alm/common/lutram_mlab.txt b/techlibs/intel_alm/common/lutram_mlab.txt
index 1d6174d85..3cc69399d 100644
--- a/techlibs/intel_alm/common/lutram_mlab.txt
+++ b/techlibs/intel_alm/common/lutram_mlab.txt
@@ -1,20 +1,18 @@
-bram __MISTRAL_MLAB
-    init   0   # TODO: Re-enable when I figure out how LUTRAM init works
-    abits  5
-    dbits  16  @D32x16
-    dbits  18  @D32x18
-    dbits  20  @D32x20
-    groups 2
-    ports  1 1
-    wrmode 1 0
-    # read enable
-    enable 1 0
-    transp 1 0
-    clocks 1 2
-    clkpol 1 1
-endbram
-
-match __MISTRAL_MLAB
-    min efficiency 5
-    make_outreg
-endmatch
+bram MISTRAL_MLAB
+    init   0   # TODO: Re-enable when Yosys remembers the original filename.
+    abits  5
+    dbits  1
+    groups 2
+    ports  1 1
+    wrmode 1 0
+    # write enable
+    enable 1 0
+    transp 0 0
+    clocks 1 0
+    clkpol 1 1
+endbram
+
+match MISTRAL_MLAB
+    min efficiency 5
+    make_outreg
+endmatch
+\ No newline at end of file
diff --git a/techlibs/intel_alm/common/lutram_mlab_map.v b/techlibs/intel_alm/common/lutram_mlab_map.v
deleted file mode 100644
index 3a9c8590e..000000000
--- a/techlibs/intel_alm/common/lutram_mlab_map.v
+++ /dev/null
@@ -1,29 +0,0 @@
-module __MISTRAL_MLAB(CLK1, CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA);
-
-parameter CFG_ABITS = 5;
-parameter CFG_DBITS = 20;
-
-input CLK1, CLK2;
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-input A1EN;
-output [CFG_DBITS-1:0] B1DATA;
-
-altsyncram #(
-    .operation_mode("dual_port"),
-    .ram_block_type("mlab"),
-    .widthad_a(CFG_ABITS),
-    .width_a(CFG_DBITS),
-    .widthad_b(CFG_ABITS),
-    .width_b(CFG_DBITS),
-) _TECHMAP_REPLACE_ (
-    .address_a(A1ADDR),
-    .data_a(A1DATA),
-    .wren_a(A1EN),
-    .address_b(B1ADDR),
-    .q_b(B1DATA),
-    .clock0(CLK1),
-    .clock1(CLK1),
-);
-
-endmodule
diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v
index 21ba73a09..c749fa70b 100644
--- a/techlibs/intel_alm/common/megafunction_bb.v
+++ b/techlibs/intel_alm/common/megafunction_bb.v
@@ -106,3 +106,26 @@ input aclr1;
 output eccstatus;
 
 endmodule
+
+(* blackbox *)
+module cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);
+
+parameter logical_ram_name = "";
+parameter logical_ram_depth = 32;
+parameter logical_ram_width = 20;
+parameter mixed_port_feed_through_mode = "new";
+parameter first_bit_number = 0;
+parameter first_address = 0;
+parameter last_address = 31;
+parameter address_width = 5;
+parameter data_width = 1;
+parameter byte_enable_mask_width = 1;
+parameter port_b_data_out_clock = "NONE";
+parameter [639:0] mem_init0 = 640'b0;
+
+input [address_width-1:0] portaaddr, portbaddr;
+input [data_width-1:0] portadatain;
+output [data_width-1:0] portbdataout;
+input ena0, clk0, clk1;
+
+endmodule
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
new file mode 100644
index 000000000..ae79b19a4
--- /dev/null
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -0,0 +1,60 @@
+// The MLAB
+// --------
+// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
+// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
+// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
+// the memory the ALM uses to store the look-up table data for general usage, 
+// producing a 32 address by 20-bit block of memory. MLABs are spread out
+// around the chip, so they can be placed near where they are needed, rather than
+// being comparatively limited in placement for a deep but narrow memory such as
+// the M10K memory block.
+//
+// MLABs are used mainly for shallow but wide memories, such as CPU register
+// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
+// or shift registers (by using the output of the Nth bit as input for the N+1th
+// bit).
+//
+// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
+// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
+// to put these cells in the same MLAB during cell placement. Because of this
+// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
+// 20 of them represent a physical MLAB.
+//
+// How the MLAB works
+// ------------------
+// MLABs are poorly documented, so the following information is based mainly
+// on the simulation model and my knowledge of how memories like these work.
+// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
+// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
+// `techmap` just for the sake of renaming the cell ports.
+//
+// The MLAB can be initialised to any value, but unfortunately Quartus only
+// allows memory initialisation from a file. Since Yosys doesn't preserve input
+// file information, or write the contents of an `initial` block to a file,
+// Yosys can't currently initialise the MLAB in a way Quartus will accept.
+//
+// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
+// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
+// conditionally write data to the MLAB.
+//
+// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
+// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
+// then the output can be fed to embedded flops. Presently, Yosys assumes
+// Quartus will pack external flops into the MLAB, but this is an assumption
+// that needs testing.
+
+// The vendor sim model outputs 'x for a very short period (a few 
+// combinational delta cycles) after each write. This has been omitted from
+// the following model because it's very difficult to trigger this in practice
+// as clock cycles will be much longer than any potential blip of 'x, so the
+// model can be treated as always returning a defined result.
+module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
+
+reg [31:0] mem = 32'b0;
+
+always @(posedge CLK1)
+    if (A1EN) mem[A1ADDR] <= A1DATA;
+
+assign B1DATA = mem[B1ADDR];
+
+endmodule
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index d9961c174..c40a4e02d 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -1,3 +1,12 @@
+`ifdef cyclonev
+`define LCELL cyclonev_lcell_comb
+`define MLAB cyclonev_mlab_cell
+`endif
+`ifdef cyclone10gx
+`define LCELL cyclone10gx_lcell_comb
+`define MLAB cyclone10gx_mlab_cell
+`endif
+
 module __MISTRAL_VCC(output Q);
 
 MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
@@ -17,3 +26,96 @@ module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q
 dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
 
 endmodule
+
+
+module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
+parameter [63:0] LUT = 64'h0000_0000_0000_0000;
+
+`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
+
+endmodule
+
+
+module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
+parameter [31:0] LUT = 32'h0000_0000;
+
+`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
+
+endmodule
+
+
+module MISTRAL_ALUT4(input A, B, C, D, output Q);
+parameter [15:0] LUT = 16'h0000;
+
+`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
+
+endmodule
+
+
+module MISTRAL_ALUT3(input A, B, C, output Q);
+parameter [7:0] LUT = 8'h00;
+
+`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
+
+endmodule
+
+
+module MISTRAL_ALUT2(input A, B, output Q);
+parameter [3:0] LUT = 4'h0;
+
+`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
+
+endmodule
+
+
+module MISTRAL_NOT(input A, output Q);
+
+NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
+
+endmodule
+
+
+module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
+parameter LUT0 = 16'h0000;
+parameter LUT1 = 16'h0000;
+
+`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
+
+endmodule
+
+
+module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
+
+// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
+// which takes in a hexadecimal string that could be used to initialise RAM.
+// In the vendor simulation models, this appears to work fine, but Quartus,
+// either intentionally or not, forgets about this parameter and initialises the
+// RAM to zero.
+//
+// Because of this, RAM initialisation is presently disabled, but the source
+// used to generate mem_init0 is kept (commented out) in case this gets fixed
+// or an undocumented way to get Quartus to initialise from mem_init0 is found.
+
+`MLAB #(
+    .logical_ram_name("MISTRAL_MLAB"),
+    .logical_ram_depth(32),
+    .logical_ram_width(1),
+    .mixed_port_feed_through_mode("Dont Care"),
+    .first_bit_number(0),
+    .first_address(0),
+    .last_address(31),
+    .address_width(5),
+    .data_width(1),
+    .byte_enable_mask_width(1),
+    .port_b_data_out_clock("NONE"),
+    // .mem_init0($sformatf("%08x", INIT))
+) _TECHMAP_REPLACE_ (
+    .portaaddr(A1ADDR),
+    .portadatain(A1DATA),
+    .portbaddr(B1ADDR),
+    .portbdataout(B1DATA),
+    .ena0(A1EN),
+    .clk0(CLK1)
+);
+
+endmodule
diff --git a/techlibs/intel_alm/cyclone10gx/quartus_rename.v b/techlibs/intel_alm/cyclone10gx/quartus_rename.v
deleted file mode 100644
index 3fbc508ed..000000000
--- a/techlibs/intel_alm/cyclone10gx/quartus_rename.v
+++ /dev/null
@@ -1,54 +0,0 @@
-module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
-parameter LUT = 64'h0000_0000_0000_0000;
-
-cyclone10gx_lcell_comb #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
-parameter LUT = 32'h0000_0000;
-
-cyclone10gx_lcell_comb #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT4(input A, B, C, D, output Q);
-parameter LUT = 16'h0000;
-
-cyclone10gx_lcell_comb #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT3(input A, B, C, output Q);
-parameter LUT = 8'h00;
-
-cyclone10gx_lcell_comb #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT2(input A, B, output Q);
-parameter LUT = 4'h0;
-
-cyclone10gx_lcell_comb #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_NOT(input A, output Q);
-
-NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
-parameter LUT0 = 16'h0000;
-parameter LUT1 = 16'h0000;
-
-cyclone10gx_lcell_comb #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
-
-endmodule
diff --git a/techlibs/intel_alm/cyclonev/quartus_rename.v b/techlibs/intel_alm/cyclonev/quartus_rename.v
deleted file mode 100644
index 6eff375e1..000000000
--- a/techlibs/intel_alm/cyclonev/quartus_rename.v
+++ /dev/null
@@ -1,54 +0,0 @@
-module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
-parameter LUT = 64'h0000_0000_0000_0000;
-
-cyclonev_lcell_comb #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
-parameter LUT = 32'h0000_0000;
-
-cyclonev_lcell_comb #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT4(input A, B, C, D, output Q);
-parameter LUT = 16'h0000;
-
-cyclonev_lcell_comb #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT3(input A, B, C, output Q);
-parameter LUT = 8'h00;
-
-cyclonev_lcell_comb #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT2(input A, B, output Q);
-parameter LUT = 4'h0;
-
-cyclonev_lcell_comb #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_NOT(input A, output Q);
-
-NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
-parameter LUT0 = 16'h0000;
-parameter LUT1 = 16'h0000;
-
-cyclonev_lcell_comb #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
-
-endmodule
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 5d4c78d74..bf9e746b8 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -164,6 +164,7 @@ struct SynthIntelALMPass : public ScriptPass {
 			run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
+			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
 
 			// Misc and common cells
 			run("read_verilog -lib +/intel/common/altpll_bb.v");
@@ -190,7 +191,6 @@ struct SynthIntelALMPass : public ScriptPass {
 
 		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
 			run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)");
-			run("techmap -map +/intel_alm/common/lutram_mlab_map.v", "(for Cyclone V / Cyclone 10GX)");
 		}
 
 		if (check_label("map_ffram")) {
@@ -235,8 +235,7 @@ struct SynthIntelALMPass : public ScriptPass {
 				// to constant driver cells, which Quartus accepts.
 				run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q");
 				// Rename from Yosys-internal MISTRAL_* cells to Quartus cells.
-				run("techmap -map +/intel_alm/common/quartus_rename.v");
-				run(stringf("techmap -map +/intel_alm/%s/quartus_rename.v", family_opt.c_str()));
+				run(stringf("techmap -D %s -map +/intel_alm/common/quartus_rename.v", family_opt.c_str()));
 			}
 		}
 
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1c190d37e..229ffcb3d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,11 +619,13 @@ struct SynthXilinxPass : public ScriptPass
 				run("techmap " + techmap_args);
 				run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
 				std::string abc9_opts;
-				auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
-				if (active_design->scratchpad.count(k))
+				std::string k = "synth_xilinx.abc9.W";
+				if (active_design && active_design->scratchpad.count(k))
 					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
-				else
+				else {
+					k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
 					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
+				}
 				if (nowidelut)
 					abc9_opts += stringf(" -maxlut %d", lut_size);
 				if (dff_mode)