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-rw-r--r--techlibs/common/synth.cc6
-rw-r--r--techlibs/ecp5/synth_ecp5.cc26
-rw-r--r--techlibs/gowin/synth_gowin.cc8
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc2
-rw-r--r--techlibs/ice40/Makefile.inc1
-rw-r--r--techlibs/ice40/ice40_ffssr.cc131
-rw-r--r--techlibs/ice40/ice40_opt.cc4
-rw-r--r--techlibs/ice40/synth_ice40.cc10
-rw-r--r--techlibs/intel/synth_intel.cc2
-rw-r--r--techlibs/intel_alm/Makefile.inc6
-rw-r--r--techlibs/intel_alm/common/bram_m10k.txt4
-rw-r--r--techlibs/intel_alm/common/bram_m10k_map.v31
-rw-r--r--techlibs/intel_alm/common/dsp_sim.v2
-rw-r--r--techlibs/intel_alm/common/megafunction_bb.v468
-rw-r--r--techlibs/intel_alm/common/mem_sim.v34
-rw-r--r--techlibs/intel_alm/common/quartus_rename.v51
-rw-r--r--techlibs/intel_alm/synth_intel_alm.cc10
-rw-r--r--techlibs/xilinx/synth_xilinx.cc29
18 files changed, 600 insertions, 225 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index b4c65e658..89d6e530e 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -220,6 +220,9 @@ struct SynthPass : public ScriptPass
run("opt_expr");
run("opt_clean");
run("check");
+ run("opt -nodffe -nosdff");
+ if (!nofsm)
+ run("fsm" + fsm_opts, " (unless -nofsm)");
run("opt");
run("wreduce");
run("peepopt");
@@ -233,9 +236,6 @@ struct SynthPass : public ScriptPass
if (!noshare)
run("share", " (unless -noshare)");
run("opt");
- if (!nofsm)
- run("fsm" + fsm_opts, " (unless -nofsm)");
- run("opt -fast");
run("memory -nomap" + memory_opts);
run("opt_clean");
}
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 46d051e44..3cee9722e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -257,6 +257,8 @@ struct SynthEcp5Pass : public ScriptPass
run("opt_expr");
run("opt_clean");
run("check");
+ run("opt -nodffe -nosdff");
+ run("fsm");
run("opt");
run("wreduce");
run("peepopt");
@@ -271,8 +273,6 @@ struct SynthEcp5Pass : public ScriptPass
}
run("alumacc");
run("opt");
- run("fsm");
- run("opt -fast");
run("memory -nomap");
run("opt_clean");
}
@@ -311,16 +311,20 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("map_ffs"))
{
- run("dff2dffs");
run("opt_clean");
- if (!nodffe)
- run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
- if (help_mode)
- run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFFE_??_ 01 -cell $_DFF_?P?_ r -cell $_DFFE_?P??_ r -cell $_SDFF_?P?_ r -cell $_SDFFE_?P??_ r -cell $_DLATCH_?_ x [-cell $_DFFSR_?PP_ x]", "($_DFFSR_*_ only if -asyncprld)");
- else if (asyncprld)
- run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFFE_??_ 01 -cell $_DFF_?P?_ r -cell $_DFFE_?P??_ r -cell $_SDFF_?P?_ r -cell $_SDFFE_?P??_ r -cell $_DLATCH_?_ x -cell $_DFFSR_?PP_ x");
- else
- run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFFE_??_ 01 -cell $_DFF_?P?_ r -cell $_DFFE_?P??_ r -cell $_SDFF_?P?_ r -cell $_SDFFE_?P??_ r -cell $_DLATCH_?_ x");
+ std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
+ if (help_mode) {
+ dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
+ } else if (!nodffe) {
+ dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
+ }
+ dfflegalize_args += " -cell $_DLATCH_?_ x";
+ if (help_mode) {
+ dfflegalize_args += " [-cell $_DFFSR_?PP_ x]";
+ } else if (asyncprld) {
+ dfflegalize_args += " -cell $_DFFSR_?PP_ x";
+ }
+ run("dfflegalize" + dfflegalize_args, "($_DFFSR_*_ only if -asyncprld, $_*DFFE_* only if not -nodffe)");
if ((abc9 && dff) || help_mode)
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff");
run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index d7b11d431..4d1e968ae 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -219,11 +219,11 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_ffs"))
{
- run("dff2dffs -match-init");
run("opt_clean");
- if (!nodffe)
- run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
- run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
+ if (nodffe)
+ run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r");
+ else
+ run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
run("techmap -map +/gowin/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 17b5d4782..d9af340d9 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -162,7 +162,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/greenpak4/cells_latch.v");
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
- run("opt -fast");
+ run("opt -fast -noclkinv -noff");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
}
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 4f4faf6d5..8ce3cb024 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -1,7 +1,6 @@
OBJS += techlibs/ice40/synth_ice40.o
OBJS += techlibs/ice40/ice40_braminit.o
-OBJS += techlibs/ice40/ice40_ffssr.o
OBJS += techlibs/ice40/ice40_opt.o
GENFILES += techlibs/ice40/brams_init1.vh
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
deleted file mode 100644
index 492029b77..000000000
--- a/techlibs/ice40/ice40_ffssr.cc
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct Ice40FfssrPass : public Pass {
- Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
- void help() override
- {
- log("\n");
- log(" ice40_ffssr [options] [selection]\n");
- log("\n");
- log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
- log("\n");
- }
- void execute(std::vector<std::string> args, RTLIL::Design *design) override
- {
- log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- // if (args[argidx] == "-singleton") {
- // singleton_mode = true;
- // continue;
- // }
- break;
- }
- extra_args(args, argidx, design);
-
- pool<IdString> sb_dff_types;
- sb_dff_types.insert(ID(SB_DFF));
- sb_dff_types.insert(ID(SB_DFFE));
- sb_dff_types.insert(ID(SB_DFFN));
- sb_dff_types.insert(ID(SB_DFFNE));
-
- for (auto module : design->selected_modules())
- {
- log("Merging set/reset $_MUX_ cells into SB_FFs in %s.\n", log_id(module));
-
- SigMap sigmap(module);
- dict<SigBit, Cell*> sr_muxes;
- vector<Cell*> ff_cells;
-
- for (auto cell : module->selected_cells())
- {
- if (sb_dff_types.count(cell->type)) {
- ff_cells.push_back(cell);
- continue;
- }
-
- if (cell->type != ID($_MUX_))
- continue;
-
- SigBit bit_a = sigmap(cell->getPort(ID::A));
- SigBit bit_b = sigmap(cell->getPort(ID::B));
-
- if (bit_a.wire == nullptr || bit_b.wire == nullptr)
- sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
- }
-
- for (auto cell : ff_cells)
- {
- if (cell->get_bool_attribute(ID(dont_touch)))
- continue;
-
- SigSpec sig_d = cell->getPort(ID::D);
-
- if (GetSize(sig_d) < 1)
- continue;
-
- SigBit bit_d = sigmap(sig_d[0]);
-
- if (sr_muxes.count(bit_d) == 0)
- continue;
-
- Cell *mux_cell = sr_muxes.at(bit_d);
- SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
- SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
- SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
-
- log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
- log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
-
- SigBit sr_val, sr_sig;
- if (bit_a.wire == nullptr) {
- bit_d = bit_b;
- sr_val = bit_a;
- sr_sig = module->NotGate(NEW_ID, bit_s);
- } else {
- log_assert(bit_b.wire == nullptr);
- bit_d = bit_a;
- sr_val = bit_b;
- sr_sig = bit_s;
- }
-
- if (sr_val == State::S1) {
- cell->type = cell->type.str() + "SS";
- cell->setPort(ID::S, sr_sig);
- cell->setPort(ID::D, bit_d);
- } else {
- cell->type = cell->type.str() + "SR";
- cell->setPort(ID::R, sr_sig);
- cell->setPort(ID::D, bit_d);
- }
- }
- }
- }
-} Ice40FfssrPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 1a70fa8c0..d28607904 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -215,7 +215,7 @@ struct Ice40OptPass : public Pass {
log(" <ice40 specific optimizations>\n");
log(" opt_expr -mux_undef -undriven [-full]\n");
log(" opt_merge\n");
- log(" opt_rmdff\n");
+ log(" opt_dff\n");
log(" opt_clean\n");
log(" while <changed design>\n");
log("\n");
@@ -247,7 +247,7 @@ struct Ice40OptPass : public Pass {
Pass::call(design, "opt_expr " + opt_expr_args);
Pass::call(design, "opt_merge");
- Pass::call(design, "opt_rmdff");
+ Pass::call(design, "opt_dff");
Pass::call(design, "opt_clean");
if (design->scratchpad_get_bool("opt.did_something") == false)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 4ddb6ca70..b945889fe 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -292,6 +292,8 @@ struct SynthIce40Pass : public ScriptPass
run("opt_expr");
run("opt_clean");
run("check");
+ run("opt -nodffe -nosdff");
+ run("fsm");
run("opt");
run("wreduce");
run("peepopt");
@@ -316,8 +318,6 @@ struct SynthIce40Pass : public ScriptPass
}
run("alumacc");
run("opt");
- run("fsm");
- run("opt -fast");
run("memory -nomap");
run("opt_clean");
}
@@ -354,11 +354,6 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("map_ffs"))
{
- if (!nodffe)
- run("dff2dffe -direct-match $_DFF_*");
- if (min_ce_use >= 0) {
- run("opt_merge");
- }
if (nodffe)
run(stringf("dfflegalize -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"));
else
@@ -366,7 +361,6 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/ice40/ff_map.v");
run("opt_expr -mux_undef");
run("simplemap");
- run("ice40_ffssr");
run("ice40_opt -full");
}
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 1fa98d098..090237722 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -202,8 +202,6 @@ struct SynthIntelPass : public ScriptPass {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
- run("dff2dffe -direct-match $_DFF_*");
- run("opt -fine");
run("techmap -map +/techmap.v");
run("opt -full");
run("clean -purge");
diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index 552f00c65..e36c81c0e 100644
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -15,9 +15,9 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/ds
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
# RAM
-bramtypes := m10k m20k
-$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype).txt)))
-$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype)_map.v)))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
# Miscellaneous
diff --git a/techlibs/intel_alm/common/bram_m10k.txt b/techlibs/intel_alm/common/bram_m10k.txt
index 837e3a330..e9355fe2c 100644
--- a/techlibs/intel_alm/common/bram_m10k.txt
+++ b/techlibs/intel_alm/common/bram_m10k.txt
@@ -1,4 +1,4 @@
-bram __MISTRAL_M10K_SDP
+bram MISTRAL_M10K
init 0 # TODO: Re-enable when I figure out how BRAM init works
abits 13 @D8192x1
dbits 1 @D8192x1
@@ -27,7 +27,7 @@ bram __MISTRAL_M10K_SDP
endbram
-match __MISTRAL_M10K_SDP
+match MISTRAL_M10K
min efficiency 5
make_transp
endmatch
diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v
deleted file mode 100644
index 061463c3e..000000000
--- a/techlibs/intel_alm/common/bram_m10k_map.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
-
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 10;
-parameter CFG_ENABLE_A = 1;
-parameter CFG_ENABLE_B = 1;
-
-input CLK1;
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-output [CFG_DBITS-1:0] B1DATA;
-input [CFG_ENABLE_A-1:0] A1EN, B1EN;
-
-altsyncram #(
- .operation_mode("dual_port"),
- .ram_block_type("m10k"),
- .widthad_a(CFG_ABITS),
- .width_a(CFG_DBITS),
- .widthad_b(CFG_ABITS),
- .width_b(CFG_DBITS),
-) _TECHMAP_REPLACE_ (
- .address_a(A1ADDR),
- .data_a(A1DATA),
- .wren_a(A1EN),
- .address_b(B1ADDR),
- .q_b(B1DATA),
- .clock0(CLK1),
- .clock1(CLK1)
-);
-
-endmodule
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v
index 7e72dab0d..45fdebb3f 100644
--- a/techlibs/intel_alm/common/dsp_sim.v
+++ b/techlibs/intel_alm/common/dsp_sim.v
@@ -1,5 +1,5 @@
(* abc9_box *)
-module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
+module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v
index b5a3d8892..530e44054 100644
--- a/techlibs/intel_alm/common/megafunction_bb.v
+++ b/techlibs/intel_alm/common/megafunction_bb.v
@@ -2,6 +2,306 @@
`default_nettype none
(* blackbox *)
+module altera_pll
+#(
+ parameter reference_clock_frequency = "0 ps",
+ parameter fractional_vco_multiplier = "false",
+ parameter pll_type = "General",
+ parameter pll_subtype = "General",
+ parameter number_of_clocks = 1,
+ parameter operation_mode = "internal feedback",
+ parameter deserialization_factor = 4,
+ parameter data_rate = 0,
+
+ parameter sim_additional_refclk_cycles_to_lock = 0,
+ parameter output_clock_frequency0 = "0 ps",
+ parameter phase_shift0 = "0 ps",
+ parameter duty_cycle0 = 50,
+
+ parameter output_clock_frequency1 = "0 ps",
+ parameter phase_shift1 = "0 ps",
+ parameter duty_cycle1 = 50,
+
+ parameter output_clock_frequency2 = "0 ps",
+ parameter phase_shift2 = "0 ps",
+ parameter duty_cycle2 = 50,
+
+ parameter output_clock_frequency3 = "0 ps",
+ parameter phase_shift3 = "0 ps",
+ parameter duty_cycle3 = 50,
+
+ parameter output_clock_frequency4 = "0 ps",
+ parameter phase_shift4 = "0 ps",
+ parameter duty_cycle4 = 50,
+
+ parameter output_clock_frequency5 = "0 ps",
+ parameter phase_shift5 = "0 ps",
+ parameter duty_cycle5 = 50,
+
+ parameter output_clock_frequency6 = "0 ps",
+ parameter phase_shift6 = "0 ps",
+ parameter duty_cycle6 = 50,
+
+ parameter output_clock_frequency7 = "0 ps",
+ parameter phase_shift7 = "0 ps",
+ parameter duty_cycle7 = 50,
+
+ parameter output_clock_frequency8 = "0 ps",
+ parameter phase_shift8 = "0 ps",
+ parameter duty_cycle8 = 50,
+
+ parameter output_clock_frequency9 = "0 ps",
+ parameter phase_shift9 = "0 ps",
+ parameter duty_cycle9 = 50,
+
+
+ parameter output_clock_frequency10 = "0 ps",
+ parameter phase_shift10 = "0 ps",
+ parameter duty_cycle10 = 50,
+
+ parameter output_clock_frequency11 = "0 ps",
+ parameter phase_shift11 = "0 ps",
+ parameter duty_cycle11 = 50,
+
+ parameter output_clock_frequency12 = "0 ps",
+ parameter phase_shift12 = "0 ps",
+ parameter duty_cycle12 = 50,
+
+ parameter output_clock_frequency13 = "0 ps",
+ parameter phase_shift13 = "0 ps",
+ parameter duty_cycle13 = 50,
+
+ parameter output_clock_frequency14 = "0 ps",
+ parameter phase_shift14 = "0 ps",
+ parameter duty_cycle14 = 50,
+
+ parameter output_clock_frequency15 = "0 ps",
+ parameter phase_shift15 = "0 ps",
+ parameter duty_cycle15 = 50,
+
+ parameter output_clock_frequency16 = "0 ps",
+ parameter phase_shift16 = "0 ps",
+ parameter duty_cycle16 = 50,
+
+ parameter output_clock_frequency17 = "0 ps",
+ parameter phase_shift17 = "0 ps",
+ parameter duty_cycle17 = 50,
+
+ parameter clock_name_0 = "",
+ parameter clock_name_1 = "",
+ parameter clock_name_2 = "",
+ parameter clock_name_3 = "",
+ parameter clock_name_4 = "",
+ parameter clock_name_5 = "",
+ parameter clock_name_6 = "",
+ parameter clock_name_7 = "",
+ parameter clock_name_8 = "",
+
+ parameter clock_name_global_0 = "false",
+ parameter clock_name_global_1 = "false",
+ parameter clock_name_global_2 = "false",
+ parameter clock_name_global_3 = "false",
+ parameter clock_name_global_4 = "false",
+ parameter clock_name_global_5 = "false",
+ parameter clock_name_global_6 = "false",
+ parameter clock_name_global_7 = "false",
+ parameter clock_name_global_8 = "false",
+
+ parameter m_cnt_hi_div = 1,
+ parameter m_cnt_lo_div = 1,
+ parameter m_cnt_bypass_en = "false",
+ parameter m_cnt_odd_div_duty_en = "false",
+ parameter n_cnt_hi_div = 1,
+ parameter n_cnt_lo_div = 1,
+ parameter n_cnt_bypass_en = "false",
+ parameter n_cnt_odd_div_duty_en = "false",
+ parameter c_cnt_hi_div0 = 1,
+ parameter c_cnt_lo_div0 = 1,
+ parameter c_cnt_bypass_en0 = "false",
+ parameter c_cnt_in_src0 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en0 = "false",
+ parameter c_cnt_prst0 = 1,
+ parameter c_cnt_ph_mux_prst0 = 0,
+ parameter c_cnt_hi_div1 = 1,
+ parameter c_cnt_lo_div1 = 1,
+ parameter c_cnt_bypass_en1 = "false",
+ parameter c_cnt_in_src1 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en1 = "false",
+ parameter c_cnt_prst1 = 1,
+ parameter c_cnt_ph_mux_prst1 = 0,
+ parameter c_cnt_hi_div2 = 1,
+ parameter c_cnt_lo_div2 = 1,
+ parameter c_cnt_bypass_en2 = "false",
+ parameter c_cnt_in_src2 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en2 = "false",
+ parameter c_cnt_prst2 = 1,
+ parameter c_cnt_ph_mux_prst2 = 0,
+ parameter c_cnt_hi_div3 = 1,
+ parameter c_cnt_lo_div3 = 1,
+ parameter c_cnt_bypass_en3 = "false",
+ parameter c_cnt_in_src3 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en3 = "false",
+ parameter c_cnt_prst3 = 1,
+ parameter c_cnt_ph_mux_prst3 = 0,
+ parameter c_cnt_hi_div4 = 1,
+ parameter c_cnt_lo_div4 = 1,
+ parameter c_cnt_bypass_en4 = "false",
+ parameter c_cnt_in_src4 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en4 = "false",
+ parameter c_cnt_prst4 = 1,
+ parameter c_cnt_ph_mux_prst4 = 0,
+ parameter c_cnt_hi_div5 = 1,
+ parameter c_cnt_lo_div5 = 1,
+ parameter c_cnt_bypass_en5 = "false",
+ parameter c_cnt_in_src5 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en5 = "false",
+ parameter c_cnt_prst5 = 1,
+ parameter c_cnt_ph_mux_prst5 = 0,
+ parameter c_cnt_hi_div6 = 1,
+ parameter c_cnt_lo_div6 = 1,
+ parameter c_cnt_bypass_en6 = "false",
+ parameter c_cnt_in_src6 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en6 = "false",
+ parameter c_cnt_prst6 = 1,
+ parameter c_cnt_ph_mux_prst6 = 0,
+ parameter c_cnt_hi_div7 = 1,
+ parameter c_cnt_lo_div7 = 1,
+ parameter c_cnt_bypass_en7 = "false",
+ parameter c_cnt_in_src7 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en7 = "false",
+ parameter c_cnt_prst7 = 1,
+ parameter c_cnt_ph_mux_prst7 = 0,
+ parameter c_cnt_hi_div8 = 1,
+ parameter c_cnt_lo_div8 = 1,
+ parameter c_cnt_bypass_en8 = "false",
+ parameter c_cnt_in_src8 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en8 = "false",
+ parameter c_cnt_prst8 = 1,
+ parameter c_cnt_ph_mux_prst8 = 0,
+ parameter c_cnt_hi_div9 = 1,
+ parameter c_cnt_lo_div9 = 1,
+ parameter c_cnt_bypass_en9 = "false",
+ parameter c_cnt_in_src9 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en9 = "false",
+ parameter c_cnt_prst9 = 1,
+ parameter c_cnt_ph_mux_prst9 = 0,
+ parameter c_cnt_hi_div10 = 1,
+ parameter c_cnt_lo_div10 = 1,
+ parameter c_cnt_bypass_en10 = "false",
+ parameter c_cnt_in_src10 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en10 = "false",
+ parameter c_cnt_prst10 = 1,
+ parameter c_cnt_ph_mux_prst10 = 0,
+ parameter c_cnt_hi_div11 = 1,
+ parameter c_cnt_lo_div11 = 1,
+ parameter c_cnt_bypass_en11 = "false",
+ parameter c_cnt_in_src11 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en11 = "false",
+ parameter c_cnt_prst11 = 1,
+ parameter c_cnt_ph_mux_prst11 = 0,
+ parameter c_cnt_hi_div12 = 1,
+ parameter c_cnt_lo_div12 = 1,
+ parameter c_cnt_bypass_en12 = "false",
+ parameter c_cnt_in_src12 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en12 = "false",
+ parameter c_cnt_prst12 = 1,
+ parameter c_cnt_ph_mux_prst12 = 0,
+ parameter c_cnt_hi_div13 = 1,
+ parameter c_cnt_lo_div13 = 1,
+ parameter c_cnt_bypass_en13 = "false",
+ parameter c_cnt_in_src13 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en13 = "false",
+ parameter c_cnt_prst13 = 1,
+ parameter c_cnt_ph_mux_prst13 = 0,
+ parameter c_cnt_hi_div14 = 1,
+ parameter c_cnt_lo_div14 = 1,
+ parameter c_cnt_bypass_en14 = "false",
+ parameter c_cnt_in_src14 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en14 = "false",
+ parameter c_cnt_prst14 = 1,
+ parameter c_cnt_ph_mux_prst14 = 0,
+ parameter c_cnt_hi_div15 = 1,
+ parameter c_cnt_lo_div15 = 1,
+ parameter c_cnt_bypass_en15 = "false",
+ parameter c_cnt_in_src15 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en15 = "false",
+ parameter c_cnt_prst15 = 1,
+ parameter c_cnt_ph_mux_prst15 = 0,
+ parameter c_cnt_hi_div16 = 1,
+ parameter c_cnt_lo_div16 = 1,
+ parameter c_cnt_bypass_en16 = "false",
+ parameter c_cnt_in_src16 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en16 = "false",
+ parameter c_cnt_prst16 = 1,
+ parameter c_cnt_ph_mux_prst16 = 0,
+ parameter c_cnt_hi_div17 = 1,
+ parameter c_cnt_lo_div17 = 1,
+ parameter c_cnt_bypass_en17 = "false",
+ parameter c_cnt_in_src17 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en17 = "false",
+ parameter c_cnt_prst17 = 1,
+ parameter c_cnt_ph_mux_prst17 = 0,
+ parameter pll_vco_div = 1,
+ parameter pll_slf_rst = "false",
+ parameter pll_bw_sel = "low",
+ parameter pll_output_clk_frequency = "0 MHz",
+ parameter pll_cp_current = 0,
+ parameter pll_bwctrl = 0,
+ parameter pll_fractional_division = 1,
+ parameter pll_fractional_cout = 24,
+ parameter pll_dsm_out_sel = "1st_order",
+ parameter mimic_fbclk_type = "gclk",
+ parameter pll_fbclk_mux_1 = "glb",
+ parameter pll_fbclk_mux_2 = "fb_1",
+ parameter pll_m_cnt_in_src = "ph_mux_clk",
+ parameter pll_vcoph_div = 1,
+ parameter refclk1_frequency = "0 MHz",
+ parameter pll_clkin_0_src = "clk_0",
+ parameter pll_clkin_1_src = "clk_0",
+ parameter pll_clk_loss_sw_en = "false",
+ parameter pll_auto_clk_sw_en = "false",
+ parameter pll_manu_clk_sw_en = "false",
+ parameter pll_clk_sw_dly = 0,
+ parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
+ parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss"
+) (
+ //input
+ input refclk,
+ input refclk1,
+ input fbclk,
+ input rst,
+ input phase_en,
+ input updn,
+ input [2:0] num_phase_shifts,
+ input scanclk,
+ input [4:0] cntsel,
+ input [63:0] reconfig_to_pll,
+ input extswitch,
+ input adjpllin,
+ input cclk,
+
+ //output
+ output [ number_of_clocks -1 : 0] outclk,
+ output fboutclk,
+ output locked,
+ output phase_done,
+ output [63:0] reconfig_from_pll,
+ output activeclk,
+ output [1:0] clkbad,
+ output [7:0] phout,
+ output [1:0] lvds_clk,
+ output [1:0] loaden,
+ output [1:0] extclk_out,
+ output [ number_of_clocks -1 : 0] cascade_out,
+
+ //inout
+ inout zdbfbclk
+);
+
+endmodule
+
+
+(* blackbox *)
module altera_std_synchronizer(clk, din, dout, reset_n);
parameter depth = 2;
@@ -14,6 +314,137 @@ output dout;
endmodule
(* blackbox *)
+module altddio_in (
+ datain, // required port, DDR input data
+ inclock, // required port, input reference clock to sample data by
+ inclocken, // enable data clock
+ aset, // asynchronous set
+ aclr, // asynchronous clear
+ sset, // synchronous set
+ sclr, // synchronous clear
+ dataout_h, // data sampled at the rising edge of inclock
+ dataout_l // data sampled at the falling edge of inclock
+);
+
+parameter width = 1;
+parameter power_up_high = "OFF";
+parameter invert_input_clocks = "OFF";
+parameter intended_device_family = "Stratix";
+parameter lpm_type = "altddio_in";
+parameter lpm_hint = "UNUSED";
+
+input [width-1:0] datain;
+input inclock;
+input inclocken;
+input aset;
+input aclr;
+input sset;
+input sclr;
+
+output [width-1:0] dataout_h;
+output [width-1:0] dataout_l;
+
+endmodule
+
+
+(* blackbox *)
+module altddio_out (
+ datain_h,
+ datain_l,
+ outclock,
+ outclocken,
+ aset,
+ aclr,
+ sset,
+ sclr,
+ oe,
+ dataout,
+ oe_out
+);
+
+parameter width = 1;
+parameter power_up_high = "OFF";
+parameter oe_reg = "UNUSED";
+parameter extend_oe_disable = "UNUSED";
+parameter intended_device_family = "Stratix";
+parameter invert_output = "OFF";
+parameter lpm_type = "altddio_out";
+parameter lpm_hint = "UNUSED";
+
+input [width-1:0] datain_h;
+input [width-1:0] datain_l;
+input outclock;
+input outclocken;
+input aset;
+input aclr;
+input sset;
+input sclr;
+input oe;
+
+output [width-1:0] dataout;
+output [width-1:0] oe_out;
+
+endmodule
+
+
+(* blackbox *)
+module altddio_bidir (
+ datain_h,
+ datain_l,
+ inclock,
+ inclocken,
+ outclock,
+ outclocken,
+ aset,
+ aclr,
+ sset,
+ sclr,
+ oe,
+ dataout_h,
+ dataout_l,
+ combout,
+ oe_out,
+ dqsundelayedout,
+ padio
+);
+
+// GLOBAL PARAMETER DECLARATION
+parameter width = 1; // required parameter
+parameter power_up_high = "OFF";
+parameter oe_reg = "UNUSED";
+parameter extend_oe_disable = "UNUSED";
+parameter implement_input_in_lcell = "UNUSED";
+parameter invert_output = "OFF";
+parameter intended_device_family = "Stratix";
+parameter lpm_type = "altddio_bidir";
+parameter lpm_hint = "UNUSED";
+
+// INPUT PORT DECLARATION
+input [width-1:0] datain_h;
+input [width-1:0] datain_l;
+input inclock;
+input inclocken;
+input outclock;
+input outclocken;
+input aset;
+input aclr;
+input sset;
+input sclr;
+input oe;
+
+// OUTPUT PORT DECLARATION
+output [width-1:0] dataout_h;
+output [width-1:0] dataout_l;
+output [width-1:0] combout;
+output [width-1:0] oe_out;
+output [width-1:0] dqsundelayedout;
+// BIDIRECTIONAL PORT DECLARATION
+inout [width-1:0] padio;
+
+endmodule
+
+
+(* blackbox *)
module altiobuf_in(datain, dataout);
parameter enable_bus_hold = "FALSE";
@@ -156,4 +587,39 @@ input [ax_width-1:0] ax;
input [ay_scan_in_width-1:0] ay;
output [result_a_width-1:0] resulta;
-endmodule \ No newline at end of file
+endmodule
+
+(* blackbox *)
+module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);
+
+parameter operation_mode = "dual_port";
+parameter logical_ram_name = "";
+parameter port_a_address_width = 10;
+parameter port_a_data_width = 10;
+parameter port_a_logical_ram_depth = 1024;
+parameter port_a_logical_ram_width = 10;
+parameter port_a_first_address = 0;
+parameter port_a_last_address = 1023;
+parameter port_a_first_bit_number = 0;
+parameter port_b_address_width = 10;
+parameter port_b_data_width = 10;
+parameter port_b_logical_ram_depth = 1024;
+parameter port_b_logical_ram_width = 10;
+parameter port_b_first_address = 0;
+parameter port_b_last_address = 1023;
+parameter port_b_first_bit_number = 0;
+parameter port_b_address_clock = "clock0";
+parameter port_b_read_enable_clock = "clock0";
+parameter mem_init0 = "";
+parameter mem_init1 = "";
+parameter mem_init2 = "";
+parameter mem_init3 = "";
+parameter mem_init4 = "";
+
+input [port_a_address_width-1:0] portaaddr;
+input [port_b_address_width-1:0] portbaddr;
+input [port_a_data_width-1:0] portadatain;
+output [port_b_data_width-1:0] portbdataout;
+input clk0, portawe, portbre;
+
+endmodule
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index b0e1763db..e09aafaa2 100644
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -73,3 +73,37 @@ always @(posedge CLK1)
assign B1DATA = mem[B1ADDR];
endmodule
+
+// The M10K
+// --------
+// TODO
+
+module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+
+input CLK1;
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+input A1EN, B1EN;
+output reg [CFG_DBITS-1:0] B1DATA;
+
+reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
+
+specify
+ $setup(A1ADDR, posedge CLK1, 0);
+ $setup(A1DATA, posedge CLK1, 0);
+
+ if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
+endspecify
+
+always @(posedge CLK1) begin
+ if (A1EN)
+ mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
+
+ if (B1EN)
+ B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
+end
+
+endmodule
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 46ef2aa0d..9bc532ca2 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -88,6 +88,8 @@ endmodule
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
+parameter _TECHMAP_CELLNAME_ = "";
+
// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
// which takes in a hexadecimal string that could be used to initialise RAM.
// In the vendor simulation models, this appears to work fine, but Quartus,
@@ -99,7 +101,7 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
// or an undocumented way to get Quartus to initialise from mem_init0 is found.
`MLAB #(
- .logical_ram_name("MISTRAL_MLAB"),
+ .logical_ram_name(_TECHMAP_CELLNAME_),
.logical_ram_depth(32),
.logical_ram_width(1),
.mixed_port_feed_through_mode("Dont Care"),
@@ -123,6 +125,53 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
endmodule
+module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+
+parameter _TECHMAP_CELLNAME_ = "";
+
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+input CLK1, A1EN, B1EN;
+output [CFG_DBITS-1:0] B1DATA;
+
+// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
+// you initialise the RAM cell via hex literals. If they were implemented.
+
+cyclonev_ram_block #(
+ .operation_mode("dual_port"),
+ .logical_ram_name(_TECHMAP_CELLNAME_),
+ .port_a_address_width(CFG_ABITS),
+ .port_a_data_width(CFG_DBITS),
+ .port_a_logical_ram_depth(2**CFG_ABITS),
+ .port_a_logical_ram_width(CFG_DBITS),
+ .port_a_first_address(0),
+ .port_a_last_address(2**CFG_ABITS - 1),
+ .port_a_first_bit_number(0),
+ .port_b_address_width(CFG_ABITS),
+ .port_b_data_width(CFG_DBITS),
+ .port_b_logical_ram_depth(2**CFG_ABITS),
+ .port_b_logical_ram_width(CFG_DBITS),
+ .port_b_first_address(0),
+ .port_b_last_address(2**CFG_ABITS - 1),
+ .port_b_first_bit_number(0),
+ .port_b_address_clock("clock0"),
+ .port_b_read_enable_clock("clock0")
+) _TECHMAP_REPLACE_ (
+ .portaaddr(A1ADDR),
+ .portadatain(A1DATA),
+ .portawe(A1EN),
+ .portbaddr(B1ADDR),
+ .portbdataout(B1DATA),
+ .portbre(B1EN),
+ .clk0(CLK1)
+);
+
+endmodule
+
+
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y));
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index b751e8413..83f0768a3 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -200,6 +200,8 @@ struct SynthIntelALMPass : public ScriptPass {
run("opt_expr");
run("opt_clean");
run("check");
+ run("opt -nodffe -nosdff");
+ run("fsm");
run("opt");
run("wreduce");
run("peepopt");
@@ -227,15 +229,14 @@ struct SynthIntelALMPass : public ScriptPass {
run("alumacc");
run("techmap -map +/intel_alm/common/arith_alm_map.v -map +/intel_alm/common/dsp_map.v");
run("opt");
- run("fsm");
- run("opt -fast");
run("memory -nomap");
run("opt_clean");
}
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
- run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
+ if (help_mode || bram_type != "m10k")
+ run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
}
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
@@ -249,7 +250,6 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("map_ffs")) {
run("techmap");
- run("dff2dffe");
run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0");
run("techmap -map +/intel_alm/common/dff_map.v");
run("opt -full -undriven -mux_undef");
@@ -258,7 +258,7 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("map_luts")) {
run("techmap -map +/intel_alm/common/abc9_map.v");
- run(stringf("abc9 %s -maxlut 6 -W 200", help_mode ? "[-dff]" : dff ? "-dff" : ""));
+ run(stringf("abc9 %s -maxlut 6 -W 600", help_mode ? "[-dff]" : dff ? "-dff" : ""));
run("techmap -map +/intel_alm/common/abc9_unmap.v");
run("techmap -map +/intel_alm/common/alm_map.v");
run("opt -fast");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 45b4f5165..0adec57a2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -357,6 +357,8 @@ struct SynthXilinxPass : public ScriptPass
run("opt_expr");
run("opt_clean");
run("check");
+ run("opt -nodffe -nosdff");
+ run("fsm");
run("opt");
if (help_mode)
run("wreduce [-keepdc]", "(option for '-widemux')");
@@ -444,8 +446,6 @@ struct SynthXilinxPass : public ScriptPass
run("alumacc");
run("share");
run("opt");
- run("fsm");
- run("opt -fast");
run("memory -nomap");
run("opt_clean");
}
@@ -504,28 +504,21 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_ffram")) {
- // Required for dff2dffs to work.
- run("simplemap t:$dff t:$adff t:$mux");
- // Needs to be done before opt -mux_bool happens.
- if (help_mode)
- run("dff2dffs [-match-init]", "(-match-init for xc6s only)");
- else if (family == "xc6s")
- run("dff2dffs -match-init");
- else
- run("dff2dffs");
- if (widemux > 0)
+ if (widemux > 0) {
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently
- else
+ } else {
run("opt -fast -full");
+ }
run("memory_map");
}
if (check_label("fine")) {
- run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
- if (help_mode)
- run("muxcover <internal options> ('-widemux' only)");
- else if (widemux > 0) {
+ if (help_mode) {
+ run("simplemap t:$mux", "('-widemux' only)");
+ run("muxcover <internal options>", "('-widemux' only)");
+ } else if (widemux > 0) {
+ run("simplemap t:$mux");
constexpr int cost_mux2 = 100;
std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
switch (widemux) {
@@ -590,7 +583,7 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_luts")) {
- run("opt_expr -mux_undef");
+ run("opt_expr -mux_undef -noclkinv");
if (flatten_before_abc)
run("flatten");
if (help_mode)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-26 21:23:37 +0000