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-rw-r--r--techlibs/xilinx/abc_map.v97
-rw-r--r--techlibs/xilinx/abc_model.v88
-rw-r--r--techlibs/xilinx/abc_unmap.v119
-rw-r--r--techlibs/xilinx/abc_xc7.box41
4 files changed, 345 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 0c85d6656..9f96d16be 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -20,6 +20,103 @@
// ============================================================================
+module FDRE (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ wire \$nextQ ;
+ \$__ABC_FDRE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_R_INVERTED(IS_R_INVERTED),
+ .CLK_POLARITY(!IS_C_INVERTED),
+ .EN_POLARITY(1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ ;
+ \$__ABC_FDRE_1 #(
+ .INIT(|0),
+ .CLK_POLARITY(1'b0),
+ .EN_POLARITY(1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ wire \$nextQ , \$currQ ;
+ \$__ABC_FDCE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_CLR_INVERTED(IS_CLR_INVERTED),
+ .CLK_POLARITY(!IS_C_INVERTED),
+ .EN_POLARITY(1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ , \$currQ ;
+ \$__ABC_FDCE_1 #(
+ .INIT(INIT),
+ .CLK_POLARITY(1'b0),
+ .EN_POLARITY(1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ wire \$nextQ , \$currQ ;
+ \$__ABC_FDPE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_PRE_INVERTED(IS_PRE_INVERTED),
+ .CLK_POLARITY(!IS_C_INVERTED),
+ .EN_POLARITY(1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ , \$currQ ;
+ \$__ABC_FDPE_1 #(
+ .INIT(INIT),
+ .CLK_POLARITY(1'b0),
+ .EN_POLARITY(1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+
module RAM32X1D (
output DPO, SPO,
input D,
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 655b993f6..d94ddb7e5 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -26,6 +26,94 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
: (S0 ? I1 : I0);
endmodule
+module \$__ABC_FF_ (input C, D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
+
+(* abc_box_id=1001, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
+ (* abc_flop_clk *) input C,
+ (* abc_flop_en *) input CE,
+ (* abc_flop_d *) input D,
+ input R, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ parameter CLK_POLARITY = !IS_C_INVERTED;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id=1002, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+ (* abc_flop_clk *) input C,
+ (* abc_flop_en *) input CE,
+ (* abc_flop_d *) input D,
+ input R, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter CLK_POLARITY = 1'b0;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+endmodule
+
+(* abc_box_id=1003, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
+ (* abc_flop_clk *) input C,
+ (* abc_flop_en *) input CE,
+ (* abc_flop_d *) input D,
+ input CLR, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter CLK_POLARITY = !IS_C_INVERTED;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1004, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+ (* abc_flop_clk *) input C,
+ (* abc_flop_en *) input CE,
+ (* abc_flop_d *) input D,
+ input CLR, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter CLK_POLARITY = 1'b0;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = (CE && !CLR) ? D : \$pastQ ;
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
+ (* abc_flop_clk *) input C,
+ (* abc_flop_en *) input CE,
+ (* abc_flop_d *) input D,
+ input PRE, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ parameter CLK_POLARITY = !IS_C_INVERTED;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1006, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+ (* abc_flop_clk *) input C,
+ (* abc_flop_en *) input CE,
+ (* abc_flop_d *) input D,
+ input PRE, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter CLK_POLARITY = 1'b0;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = (CE && !PRE) ? D : \$pastQ ;
+endmodule
+
(* abc_box_id=2000 *)
module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index f101a22d0..c24571747 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -20,6 +20,125 @@
// ============================================================================
+module \$__ABC_ASYNC (input A, S, output Y);
+ assign Y = A;
+endmodule
+
+module \$__ABC_FDRE (output Q,
+ input C,
+ input CE,
+ input D,
+ input R, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ parameter CLK_POLARITY = !IS_C_INVERTED;
+ parameter EN_POLARITY = 1'b1;
+
+ FDRE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_R_INVERTED(IS_R_INVERTED),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+ );
+endmodule
+
+module \$__ABC_FDRE_1 (output Q,
+ input C,
+ input CE,
+ input D,
+ input R, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter CLK_POLARITY = 1'b0;
+ parameter EN_POLARITY = 1'b1;
+ assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+
+ FDRE_1 #(
+ .INIT(INIT),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+ );
+endmodule
+
+module \$__ABC_FDCE (output Q,
+ input C,
+ input CE,
+ input D,
+ input CLR, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter CLK_POLARITY = !IS_C_INVERTED;
+ parameter EN_POLARITY = 1'b1;
+
+ FDCE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_CLR_INVERTED(IS_CLR_INVERTED),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+ );
+endmodule
+
+module \$__ABC_FDCE_1 (output Q,
+ input C,
+ input CE,
+ input D,
+ input CLR, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter CLK_POLARITY = 1'b0;
+ parameter EN_POLARITY = 1'b1;
+
+ FDCE_1 #(
+ .INIT(INIT),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+ );
+endmodule
+
+module \$__ABC_FDPE (output Q,
+ input C,
+ input CE,
+ input D,
+ input PRE, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ parameter CLK_POLARITY = !IS_C_INVERTED;
+ parameter EN_POLARITY = 1'b1;
+
+ FDPE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_PRE_INVERTED(IS_PRE_INVERTED),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+ );
+endmodule
+
+module \$__ABC_FDPE_1 (output Q,
+ input C,
+ input CE,
+ input D,
+ input PRE, \$pastQ );
+ parameter [0:0] INIT = 1'b0;
+ parameter CLK_POLARITY = 1'b0;
+ parameter EN_POLARITY = 1'b1;
+
+ FDPE_1 #(
+ .INIT(INIT),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+ );
+endmodule
+
module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 20da3b8a0..aebb8b975 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -41,6 +41,47 @@ CARRY4 4 1 10 8
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
+# Box to emulate async behaviour of FD[CP]*
+# Inputs: A S
+# Outputs: Y
+$__ABC_ASYNC 1000 0 2 1
+0 764
+
+# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
+# reflect the -46ps Tsu
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
+FDRE 1001 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
+FDRE_1 1002 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE 1003 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE_1 1004 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE 1005 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
+0 151 0 806 0
+
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Necessary since RAMD* and SRL* have both combinatorial (i.e.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-26 14:00:17 +0000