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-rw-r--r--techlibs/common/gate2lut.v2
-rw-r--r--techlibs/ecp5/brams_map.v2
-rw-r--r--techlibs/ice40/cells_sim.v13
3 files changed, 9 insertions, 8 deletions
diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
index 99c123f4a..15cea3d8d 100644
--- a/techlibs/common/gate2lut.v
+++ b/techlibs/common/gate2lut.v
@@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y);
// A 1010 1010
// B 1100 1100
// S 1111 0000
- .LUT(8'b_1100_1010)
+ .LUT(8'b 1100_1010)
) lut (
.A(AA),
.Y(Y)
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 310aedaf2..edda17c02 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -137,8 +137,6 @@ module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN
localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
- localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
-
PDPW16KD #(
`include "bram_init_9_18_36.vh"
.DATA_WIDTH_W(36),
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 17fe2ec99..aa1d7aa86 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2350,16 +2350,19 @@ module SB_SPRAM256KA (
if (off) begin
DATAOUT <= 0;
end else
- if (CHIPSELECT && !STANDBY && !WREN) begin
- DATAOUT <= mem[ADDRESS];
- end else begin
- if (CHIPSELECT && !STANDBY && WREN) begin
+ if (STANDBY) begin
+ DATAOUT <= 'bx;
+ end else
+ if (CHIPSELECT) begin
+ if (!WREN) begin
+ DATAOUT <= mem[ADDRESS];
+ end else begin
if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
+ DATAOUT <= 'bx;
end
- DATAOUT <= 'bx;
end
end
`endif