2 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 7d1b37fd6..50eab5dde 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1126,6 +1126,7 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
+	`ABC9_ARRIVAL_U(1821)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207
 	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 204fa883f..15d12c89f 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -42,7 +42,7 @@ endmodule
 // Box to emulate async behaviour of FDP*
 (* abc9_box_id = 1001, lib_whitebox *)
 module \$__ABC9_ASYNC1 (input A, S, output Y);
-  assign Y = S ? 1'b0 : A;
+  assign Y = S ? 1'b1 : A;
 endmodule
 
 // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}