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-rw-r--r--techlibs/ecp5/ecp5_gsr.cc2
-rw-r--r--techlibs/xilinx/xilinx_dffopt.cc9
2 files changed, 7 insertions, 4 deletions
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
index 1c69e1d79..3d3f8e1c1 100644
--- a/techlibs/ecp5/ecp5_gsr.cc
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -81,7 +81,7 @@ struct Ecp5GsrPass : public Pass {
for (auto cell : module->selected_cells())
{
- if (cell->getParam(ID(GSR)).decode_string() != "AUTO")
+ if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
continue;
bool gsren = found_gsr;
diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
index c608db883..c9d63c9f7 100644
--- a/techlibs/xilinx/xilinx_dffopt.cc
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -292,18 +292,21 @@ unmap:
LutData final_lut;
if (worthy_post_r) {
final_lut = lut_d_post_r;
- log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
} else if (worthy_post_s) {
final_lut = lut_d_post_s;
- log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
} else if (worthy_post_ce) {
final_lut = lut_d_post_ce;
- log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
} else {
// Nothing to do here.
continue;
}
+ std::string ports;
+ if (worthy_post_r) ports += " + R";
+ if (worthy_post_s) ports += " + S";
+ if (worthy_post_ce) ports += " + CE";
+ log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {
cell->unsetParam(ID(IS_R_INVERTED));