aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/fabulous/Makefile.inc1
-rw-r--r--techlibs/fabulous/arith_map.v65
-rw-r--r--techlibs/fabulous/prims.v20
-rw-r--r--techlibs/fabulous/synth_fabulous.cc15
-rw-r--r--techlibs/gatemate/cells_bb.v9
-rw-r--r--techlibs/gatemate/cells_sim.v24
-rw-r--r--techlibs/gowin/cells_sim.v8
-rw-r--r--techlibs/xilinx/cells_sim.v2
8 files changed, 126 insertions, 18 deletions
diff --git a/techlibs/fabulous/Makefile.inc b/techlibs/fabulous/Makefile.inc
index 44d57542b..28b0d5ef0 100644
--- a/techlibs/fabulous/Makefile.inc
+++ b/techlibs/fabulous/Makefile.inc
@@ -8,3 +8,4 @@ $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v))
diff --git a/techlibs/fabulous/arith_map.v b/techlibs/fabulous/arith_map.v
new file mode 100644
index 000000000..eca968556
--- /dev/null
+++ b/techlibs/fabulous/arith_map.v
@@ -0,0 +1,65 @@
+`default_nettype none
+
+`ifdef ARITH_ha
+(* techmap_celltype = "$alu" *)
+module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+parameter _TECHMAP_CONSTMSK_CI_ = 0;
+parameter _TECHMAP_CONSTVAL_CI_ = 0;
+
+(* force_downto *)
+input [A_WIDTH-1:0] A;
+(* force_downto *)
+input [B_WIDTH-1:0] B;
+input CI, BI;
+(* force_downto *)
+output [Y_WIDTH-1:0] X, Y, CO;
+
+(* force_downto *)
+wire [Y_WIDTH-1:0] A_buf, B_buf;
+\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+(* force_downto *)
+wire [Y_WIDTH-1:0] AA = A_buf;
+(* force_downto *)
+wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+wire [Y_WIDTH:0] CARRY;
+
+
+LUT4_HA #(
+ .INIT(16'b0),
+ .I0MUX(1'b1)
+) carry_statrt (
+ .I0(), .I1(CI), .I2(CI), .I3(),
+ .Ci(),
+ .Co(CARRY[0])
+);
+
+// Carry chain
+genvar i;
+generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+ LUT4_HA #(
+ .INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
+ .I0MUX(1'b1)
+ ) lut_i (
+ .I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
+ .Ci(CARRY[i]),
+ .O(Y[i]),
+ .Co(CARRY[i+1])
+ );
+
+ assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
+end endgenerate
+
+assign X = AA ^ BB;
+
+endmodule
+`endif
+
diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v
index 8ddae5beb..fe3e8536a 100644
--- a/techlibs/fabulous/prims.v
+++ b/techlibs/fabulous/prims.v
@@ -24,6 +24,20 @@ module LUT4(output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
+module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
+ parameter [15:0] INIT = 0;
+ parameter I0MUX = 1'b1;
+
+ wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+ wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+
+ wire I0_sel = I0MUX ? Ci : I0;
+ assign O = I0_sel ? s1[1] : s1[0];
+
+ assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
+endmodule
+
module LUTFF(input CLK, D, output reg O);
initial O = 1'b0;
always @ (posedge CLK) begin
@@ -93,13 +107,13 @@ module Global_Clock (output CLK);
endmodule
(* blackbox, keep *)
-module InPass4_frame_config (output O0, O1, O2, O3);
+module InPass4_frame_config (input CLK, output O0, O1, O2, O3);
endmodule
(* blackbox, keep *)
-module OutPass4_frame_config (input I0, I1, I2, I3);
+module OutPass4_frame_config (input CLK, I0, I1, I2, I3);
endmodule
@@ -414,4 +428,4 @@ module LUTFF_ESS (
O <= D;
end
endmodule
-`endif // COMPLEX_DFF \ No newline at end of file
+`endif // COMPLEX_DFF
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index d7c45e094..b4a7ab2dc 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -83,6 +83,9 @@ struct SynthPass : public ScriptPass
log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
log(" their direct form ($add, $sub, etc.).\n");
log("\n");
+ log(" -carry <none|ha>\n");
+ log(" carry mapping style (none, half-adders, ...) default=none\n");
+ log("\n");
log(" -noregfile\n");
log(" do not map register files\n");
log("\n");
@@ -119,7 +122,7 @@ struct SynthPass : public ScriptPass
log("\n");
}
- string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
+ string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode;
std::vector<string> extra_plib, extra_map;
bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
@@ -137,6 +140,7 @@ struct SynthPass : public ScriptPass
noshare = false;
iopad = false;
complexdff = false;
+ carry_mode = "none";
flatten = true;
json_file = "";
blif_file = "";
@@ -229,6 +233,12 @@ struct SynthPass : public ScriptPass
complexdff = true;
continue;
}
+ if (args[argidx] == "-carry") {
+ carry_mode = args[++argidx];
+ if (carry_mode != "none" && carry_mode != "ha")
+ log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str());
+ continue;
+ }
if (args[argidx] == "-noflatten") {
flatten = false;
continue;
@@ -326,7 +336,8 @@ struct SynthPass : public ScriptPass
if (check_label("map_gates")) {
run("opt -full");
- run("techmap -map +/techmap.v");
+ run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s",
+ help_mode ? "<carry>" : carry_mode.c_str()));
run("opt -fast");
}
diff --git a/techlibs/gatemate/cells_bb.v b/techlibs/gatemate/cells_bb.v
index f6fe6a3e1..87b91764f 100644
--- a/techlibs/gatemate/cells_bb.v
+++ b/techlibs/gatemate/cells_bb.v
@@ -22,6 +22,9 @@ module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
+ parameter LOCK_REQ = 1,
+ parameter CLK270_DOUB = 0,
+ parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
@@ -123,6 +126,12 @@ module CC_CFG_CTRL(
);
endmodule
+(* blackbox *) (* keep *)
+module CC_USR_RSTN (
+ output USR_RSTN
+);
+endmodule
+
(* blackbox *)
module CC_FIFO_40K (
output A_ECC_1B_ERR,
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v
index 7e88fd7cf..7ed6d83ff 100644
--- a/techlibs/gatemate/cells_sim.v
+++ b/techlibs/gatemate/cells_sim.v
@@ -114,10 +114,10 @@ module CC_LVDS_IBUF #(
parameter [0:0] FF_IBF = 1'bx
)(
(* iopad_external_pin *)
- input IP, IN,
+ input I_P, I_N,
output Y
);
- assign Y = IP;
+ assign Y = I_P;
endmodule
@@ -133,10 +133,10 @@ module CC_LVDS_OBUF #(
)(
input A,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = A;
- assign ON = ~A;
+ assign O_P = A;
+ assign O_N = ~A;
endmodule
@@ -152,10 +152,10 @@ module CC_LVDS_TOBUF #(
)(
input A, T,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = T ? 1'bz : A;
- assign ON = T ? 1'bz : ~A;
+ assign O_P = T ? 1'bz : A;
+ assign O_N = T ? 1'bz : ~A;
endmodule
@@ -174,12 +174,12 @@ module CC_LVDS_IOBUF #(
)(
input A, T,
(* iopad_external_pin *)
- inout IOP, ION,
+ inout IO_P, IO_N,
output Y
);
- assign IOP = T ? 1'bz : A;
- assign ION = T ? 1'bz : ~A;
- assign Y = IOP;
+ assign IO_P = T ? 1'bz : A;
+ assign IO_N = T ? 1'bz : ~A;
+ assign Y = IO_P;
endmodule
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 73bf400c0..535fd05ed 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -582,6 +582,14 @@ module IOBUF (O, IO, I, OEN);
assign I = IO;
endmodule
+module ELVDS_OBUF (I, O, OB);
+ input I;
+ output O;
+ output OB;
+ assign O = I;
+ assign OB = ~I;
+endmodule
+
module TLVDS_OBUF (I, O, OB);
input I;
output O;
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ee5a89e22..e6e15b16e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -3614,7 +3614,7 @@ module DSP48E1 (
if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
else always @* Cr <= C;
- if (CREG == 1) initial Dr = 25'b0;
+ if (DREG == 1) initial Dr = 25'b0;
if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
else always @* Dr <= D;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 15:52:34 +0000