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-rw-r--r--techlibs/intel_alm/common/alm_sim.v80
-rw-r--r--techlibs/intel_alm/common/dff_sim.v55
-rw-r--r--techlibs/intel_alm/common/dsp_sim.v15
-rw-r--r--techlibs/intel_alm/common/mem_sim.v13
-rw-r--r--techlibs/xilinx/arith_map.v114
-rw-r--r--techlibs/xilinx/cells_sim.v23
-rw-r--r--techlibs/xilinx/synth_xilinx.cc15
7 files changed, 93 insertions, 222 deletions
diff --git a/techlibs/intel_alm/common/alm_sim.v b/techlibs/intel_alm/common/alm_sim.v
index 979c51132..906a95b0b 100644
--- a/techlibs/intel_alm/common/alm_sim.v
+++ b/techlibs/intel_alm/common/alm_sim.v
@@ -69,6 +69,14 @@
`default_nettype none
+// Cyclone V LUT output timings (picoseconds):
+//
+// CARRY A B C D E F G
+// COMBOUT - 605 583 510 512 - 97 400 (LUT6)
+// COMBOUT - 602 583 457 510 302 93 483 (LUT7)
+// SUMOUT 368 1342 1323 887 927 - 785 -
+// CARRYOUT 71 1082 1062 866 813 - 1198 -
+
(* abc9_lut=2, lib_whitebox *)
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
@@ -76,12 +84,12 @@ parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`ifdef cyclonev
specify
- (A => Q) = 602;
- (B => Q) = 584;
+ (A => Q) = 605;
+ (B => Q) = 583;
(C => Q) = 510;
- (D => Q) = 510;
- (E => Q) = 339;
- (F => Q) = 94;
+ (D => Q) = 512;
+ (E => Q) = 400;
+ (F => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -107,11 +115,11 @@ parameter [31:0] LUT = 32'h0000_0000;
`ifdef cyclonev
specify
- (A => Q) = 584;
+ (A => Q) = 583;
(B => Q) = 510;
- (C => Q) = 510;
- (D => Q) = 339;
- (E => Q) = 94;
+ (C => Q) = 512;
+ (D => Q) = 400;
+ (E => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -137,9 +145,9 @@ parameter [15:0] LUT = 16'h0000;
`ifdef cyclonev
specify
(A => Q) = 510;
- (B => Q) = 510;
- (C => Q) = 339;
- (D => Q) = 94;
+ (B => Q) = 512;
+ (C => Q) = 400;
+ (D => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -164,8 +172,8 @@ parameter [7:0] LUT = 8'h00;
`ifdef cyclonev
specify
(A => Q) = 510;
- (B => Q) = 339;
- (C => Q) = 94;
+ (B => Q) = 400;
+ (C => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -188,8 +196,8 @@ parameter [3:0] LUT = 4'h0;
`ifdef cyclonev
specify
- (A => Q) = 339;
- (B => Q) = 94;
+ (A => Q) = 400;
+ (B => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -209,7 +217,7 @@ module MISTRAL_NOT(input A, output Q);
`ifdef cyclonev
specify
- (A => Q) = 94;
+ (A => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -230,31 +238,33 @@ parameter LUT1 = 16'h0000;
`ifdef cyclonev
specify
- (A => SO) = 1283;
- (B => SO) = 1167;
- (C => SO) = 866;
- (D0 => SO) = 756;
- (D1 => SO) = 756;
- (CI => SO) = 355;
- (A => CO) = 950;
- (B => CO) = 1039;
- (C => CO) = 820;
- (D0 => CO) = 1006;
- (D1 => CO) = 1006;
- (CI => CO) = 23;
+ (A => SO) = 1342;
+ (B => SO) = 1323;
+ (C => SO) = 927;
+ (D0 => SO) = 887;
+ (D1 => SO) = 785;
+ (CI => SO) = 368;
+
+ (A => CO) = 1082;
+ (B => CO) = 1062;
+ (C => CO) = 813;
+ (D0 => CO) = 866;
+ (D1 => CO) = 1198;
+ (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
endspecify
`endif
`ifdef cyclone10gx
specify
- (A => SO) = 644;
- (B => SO) = 477;
- (C => SO) = 416;
+ (A => SO) = 644;
+ (B => SO) = 477;
+ (C => SO) = 416;
(D0 => SO) = 380;
(D1 => SO) = 431;
(CI => SO) = 276;
- (A => CO) = 525;
- (B => CO) = 433;
- (C => CO) = 712;
+
+ (A => CO) = 525;
+ (B => CO) = 433;
+ (C => CO) = 712;
(D0 => CO) = 653;
(D1 => CO) = 593;
(CI => CO) = 16;
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index 9ff8f9f67..d2cff0adb 100644
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -54,43 +54,44 @@
//
// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
-`ifdef cyclonev
-`define SYNCPATH 262
-`define SYNCSETUP 522
-`define COMBPATH 0
-`endif
-`ifdef cyclone10gx
-`define SYNCPATH 219
-`define SYNCSETUP 268
-`define COMBPATH 0
-`endif
-
-// fallback for when a family isn't detected (e.g. when techmapping for equivalence)
-`ifndef SYNCPATH
-`define SYNCPATH 0
-`define SYNCSETUP 0
-`define COMBPATH 0
-`endif
-
(* abc9_box, lib_whitebox *)
module MISTRAL_FF(
input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
output reg Q
);
+`ifdef cyclonev
specify
- if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = `SYNCPATH;
- if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = `SYNCPATH;
- if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = `SYNCPATH;
+ if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
+ if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
+ if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;
- $setup(DATAIN, posedge CLK, `SYNCSETUP);
- $setup(ENA, posedge CLK, `SYNCSETUP);
- $setup(SCLR, posedge CLK, `SYNCSETUP);
- $setup(SLOAD, posedge CLK, `SYNCSETUP);
- $setup(SDATA, posedge CLK, `SYNCSETUP);
+ $setup(DATAIN, posedge CLK, /* -196 */ 0);
+ $setup(ENA, posedge CLK, /* -196 */ 0);
+ $setup(SCLR, posedge CLK, /* -196 */ 0);
+ $setup(SLOAD, posedge CLK, /* -196 */ 0);
+ $setup(SDATA, posedge CLK, /* -196 */ 0);
- if (ACLR === 1'b0) (ACLR => Q) = `COMBPATH;
+ if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
+`endif
+`ifdef cyclone10gx
+specify
+ // TODO (long-term): investigate these numbers.
+ // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
+ if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
+ if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
+ if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
+
+ $setup(DATAIN, posedge CLK, 268);
+ $setup(ENA, posedge CLK, 268);
+ $setup(SCLR, posedge CLK, 268);
+ $setup(SLOAD, posedge CLK, 268);
+ $setup(SDATA, posedge CLK, 268);
+
+ if (ACLR === 1'b0) (ACLR => Q) = 0;
+endspecify
+`endif
initial begin
// Altera flops initialise to zero.
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v
index 5dc4c02de..7e72dab0d 100644
--- a/techlibs/intel_alm/common/dsp_sim.v
+++ b/techlibs/intel_alm/common/dsp_sim.v
@@ -1,9 +1,10 @@
(* abc9_box *)
module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
+// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
- (A *> Y) = 4057;
- (B *> Y) = 4057;
+ (A *> Y) = 3732;
+ (B *> Y) = 3928;
endspecify
assign Y = $signed(A) * $signed(B);
@@ -13,9 +14,10 @@ endmodule
(* abc9_box *)
module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
+// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
- (A *> Y) = 4057;
- (B *> Y) = 4057;
+ (A *> Y) = 3180;
+ (B *> Y) = 3982;
endspecify
assign Y = $signed(A) * $signed(B);
@@ -25,9 +27,10 @@ endmodule
(* abc9_box *)
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
+// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
- (A *> Y) = 4057;
- (B *> Y) = 4057;
+ (A *> Y) = 2818;
+ (B *> Y) = 3051;
endspecify
assign Y = $signed(A) * $signed(B);
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index f6f9ecb02..b0e1763db 100644
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -54,12 +54,17 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
reg [31:0] mem = 32'b0;
-// TODO
+// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
- $setup(A1ADDR, posedge CLK1, 0);
- $setup(A1DATA, posedge CLK1, 0);
+ $setup(A1ADDR, posedge CLK1, 86);
+ $setup(A1DATA, posedge CLK1, 86);
+ $setup(A1EN, posedge CLK1, 86);
- (B1ADDR *> B1DATA) = 0;
+ (B1ADDR[0] => B1DATA) = 487;
+ (B1ADDR[1] => B1DATA) = 475;
+ (B1ADDR[2] => B1DATA) = 382;
+ (B1ADDR[3] => B1DATA) = 284;
+ (B1ADDR[4] => B1DATA) = 96;
endspecify
always @(posedge CLK1)
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index 2fc216908..eb8a04bde 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -35,13 +35,7 @@ module _80_xilinx_lcu (P, G, CI, CO);
genvar i;
-`ifdef _EXPLICIT_CARRY
- localparam EXPLICIT_CARRY = 1'b1;
-`else
- localparam EXPLICIT_CARRY = 1'b0;
-`endif
-
-generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
+generate if (`LUT_SIZE == 4) begin
(* force_downto *)
wire [WIDTH-1:0] C = {CO, CI};
@@ -135,12 +129,6 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
genvar i;
-`ifdef _EXPLICIT_CARRY
- localparam EXPLICIT_CARRY = 1'b1;
-`else
- localparam EXPLICIT_CARRY = 1'b0;
-`endif
-
generate if (`LUT_SIZE == 4) begin
(* force_downto *)
@@ -163,106 +151,6 @@ generate if (`LUT_SIZE == 4) begin
);
end endgenerate
-end else if (EXPLICIT_CARRY) begin
-
- (* force_downto *)
- wire [Y_WIDTH-1:0] S = AA ^ BB;
-
- wire CINIT;
- // Carry chain.
- //
- // VPR requires that the carry chain never hit the fabric. The CO input
- // to this techmap is the carry outputs for synthesis, e.g. might hit the
- // fabric.
- //
- // So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
- // e.g. off fabric dedicated chain. CO is the carry outputs that are
- // available to the fabric.
- (* force_downto *)
- wire [Y_WIDTH-1:0] CO_CHAIN;
- (* force_downto *)
- wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
-
- // If carry chain is being initialized to a constant, techmap the constant
- // source. Otherwise techmap the fabric source.
- generate for (i = 0; i < 1; i = i + 1) begin:slice
- CARRY0 #(.CYINIT_FABRIC(1)) carry(
- .CI_INIT(CI),
- .DI(AA[0]),
- .S(S[0]),
- .CO_CHAIN(CO_CHAIN[0]),
- .CO_FABRIC(CO[0]),
- .O(Y[0])
- );
- end endgenerate
-
- generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
- if(i % 4 == 0) begin
- CARRY0 carry (
- .CI(C[i]),
- .DI(AA[i]),
- .S(S[i]),
- .CO_CHAIN(CO_CHAIN[i]),
- .CO_FABRIC(CO[i]),
- .O(Y[i])
- );
- end
- else
- begin
- CARRY carry (
- .CI(C[i]),
- .DI(AA[i]),
- .S(S[i]),
- .CO_CHAIN(CO_CHAIN[i]),
- .CO_FABRIC(CO[i]),
- .O(Y[i])
- );
- end
- end endgenerate
-
- generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
- if(i % 4 == 0) begin
- CARRY0 top_of_carry (
- .CI(C[i]),
- .DI(AA[i]),
- .S(S[i]),
- .CO_CHAIN(CO_CHAIN[i]),
- .O(Y[i])
- );
- end
- else
- begin
- CARRY top_of_carry (
- .CI(C[i]),
- .DI(AA[i]),
- .S(S[i]),
- .CO_CHAIN(CO_CHAIN[i]),
- .O(Y[i])
- );
- end
- // Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
- // a non-congested path to output the top of the carry chain.
- // Registering the output of the CARRY block would solve this, but not
- // all designs do that.
- if((i+1) % 4 == 0) begin
- CARRY0 carry_output (
- .CI(CO_CHAIN[i]),
- .DI(0),
- .S(0),
- .O(CO[i])
- );
- end
- else
- begin
- CARRY carry_output (
- .CI(CO_CHAIN[i]),
- .DI(0),
- .S(0),
- .O(CO[i])
- );
- end
- end endgenerate
-
end else begin
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index f5850d8a2..a04587e87 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -455,29 +455,6 @@ module CARRY8(
assign CO[7] = S[7] ? CO[6] : DI[7];
endmodule
-`ifdef _EXPLICIT_CARRY
-
-module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
- parameter CYINIT_FABRIC = 0;
- wire CI_COMBINE;
- if(CYINIT_FABRIC) begin
- assign CI_COMBINE = CI_INIT;
- end else begin
- assign CI_COMBINE = CI;
- end
- assign CO_CHAIN = S ? CI_COMBINE : DI;
- assign CO_FABRIC = S ? CI_COMBINE : DI;
- assign O = S ^ CI_COMBINE;
-endmodule
-
-module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
- assign CO_CHAIN = S ? CI : DI;
- assign CO_FABRIC = S ? CI : DI;
- assign O = S ^ CI;
-endmodule
-
-`endif
-
module ORCY (output O, input CI, I);
assign O = CI | I;
endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 421602e62..45b4f5165 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -77,10 +77,6 @@ struct SynthXilinxPass : public ScriptPass
log(" write the design to the specified BLIF file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
- log(" -vpr\n");
- log(" generate an output netlist (and BLIF file) suitable for VPR\n");
- log(" (this feature is experimental and incomplete)\n");
- log("\n");
log(" -ise\n");
log(" generate an output netlist suitable for ISE\n");
log("\n");
@@ -142,7 +138,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
- bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
+ bool flatten, retime, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
bool abc9, dff;
bool flatten_before_abc;
int widemux;
@@ -157,7 +153,6 @@ struct SynthXilinxPass : public ScriptPass
family = "xc7";
flatten = false;
retime = false;
- vpr = false;
ise = false;
noiopad = false;
noclkbuf = false;
@@ -229,10 +224,6 @@ struct SynthXilinxPass : public ScriptPass
nowidelut = true;
continue;
}
- if (args[argidx] == "-vpr") {
- vpr = true;
- continue;
- }
if (args[argidx] == "-ise") {
ise = true;
continue;
@@ -345,8 +336,6 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("begin")) {
std::string read_args;
- if (vpr)
- read_args += " -D_EXPLICIT_CARRY";
read_args += " -lib -specify +/xilinx/cells_sim.v";
run("read_verilog" + read_args);
@@ -570,8 +559,6 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
if (!nocarry) {
techmap_args += " -map +/xilinx/arith_map.v";
- if (vpr)
- techmap_args += " -D _EXPLICIT_CARRY";
}
run("techmap " + techmap_args);
run("opt -fast");
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-25 11:33:28 +0000