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-rw-r--r--techlibs/fabulous/Makefile.inc1
-rw-r--r--techlibs/fabulous/arith_map.v65
-rw-r--r--techlibs/fabulous/prims.v14
-rw-r--r--techlibs/fabulous/synth_fabulous.cc15
-rw-r--r--techlibs/gatemate/cells_sim.v12
-rw-r--r--techlibs/gatemate/reg_map.v10
-rw-r--r--techlibs/gatemate/synth_gatemate.cc2
-rw-r--r--techlibs/gowin/cells_sim.v25
-rw-r--r--techlibs/ice40/cells_sim.v28
9 files changed, 148 insertions, 24 deletions
diff --git a/techlibs/fabulous/Makefile.inc b/techlibs/fabulous/Makefile.inc
index 44d57542b..28b0d5ef0 100644
--- a/techlibs/fabulous/Makefile.inc
+++ b/techlibs/fabulous/Makefile.inc
@@ -8,3 +8,4 @@ $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v))
diff --git a/techlibs/fabulous/arith_map.v b/techlibs/fabulous/arith_map.v
new file mode 100644
index 000000000..eca968556
--- /dev/null
+++ b/techlibs/fabulous/arith_map.v
@@ -0,0 +1,65 @@
+`default_nettype none
+
+`ifdef ARITH_ha
+(* techmap_celltype = "$alu" *)
+module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+parameter _TECHMAP_CONSTMSK_CI_ = 0;
+parameter _TECHMAP_CONSTVAL_CI_ = 0;
+
+(* force_downto *)
+input [A_WIDTH-1:0] A;
+(* force_downto *)
+input [B_WIDTH-1:0] B;
+input CI, BI;
+(* force_downto *)
+output [Y_WIDTH-1:0] X, Y, CO;
+
+(* force_downto *)
+wire [Y_WIDTH-1:0] A_buf, B_buf;
+\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+(* force_downto *)
+wire [Y_WIDTH-1:0] AA = A_buf;
+(* force_downto *)
+wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+wire [Y_WIDTH:0] CARRY;
+
+
+LUT4_HA #(
+ .INIT(16'b0),
+ .I0MUX(1'b1)
+) carry_statrt (
+ .I0(), .I1(CI), .I2(CI), .I3(),
+ .Ci(),
+ .Co(CARRY[0])
+);
+
+// Carry chain
+genvar i;
+generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+ LUT4_HA #(
+ .INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
+ .I0MUX(1'b1)
+ ) lut_i (
+ .I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
+ .Ci(CARRY[i]),
+ .O(Y[i]),
+ .Co(CARRY[i+1])
+ );
+
+ assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
+end endgenerate
+
+assign X = AA ^ BB;
+
+endmodule
+`endif
+
diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v
index bd0af906a..fe3e8536a 100644
--- a/techlibs/fabulous/prims.v
+++ b/techlibs/fabulous/prims.v
@@ -24,6 +24,20 @@ module LUT4(output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
+module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
+ parameter [15:0] INIT = 0;
+ parameter I0MUX = 1'b1;
+
+ wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+ wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+
+ wire I0_sel = I0MUX ? Ci : I0;
+ assign O = I0_sel ? s1[1] : s1[0];
+
+ assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
+endmodule
+
module LUTFF(input CLK, D, output reg O);
initial O = 1'b0;
always @ (posedge CLK) begin
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index d7c45e094..b4a7ab2dc 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -83,6 +83,9 @@ struct SynthPass : public ScriptPass
log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
log(" their direct form ($add, $sub, etc.).\n");
log("\n");
+ log(" -carry <none|ha>\n");
+ log(" carry mapping style (none, half-adders, ...) default=none\n");
+ log("\n");
log(" -noregfile\n");
log(" do not map register files\n");
log("\n");
@@ -119,7 +122,7 @@ struct SynthPass : public ScriptPass
log("\n");
}
- string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
+ string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode;
std::vector<string> extra_plib, extra_map;
bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
@@ -137,6 +140,7 @@ struct SynthPass : public ScriptPass
noshare = false;
iopad = false;
complexdff = false;
+ carry_mode = "none";
flatten = true;
json_file = "";
blif_file = "";
@@ -229,6 +233,12 @@ struct SynthPass : public ScriptPass
complexdff = true;
continue;
}
+ if (args[argidx] == "-carry") {
+ carry_mode = args[++argidx];
+ if (carry_mode != "none" && carry_mode != "ha")
+ log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str());
+ continue;
+ }
if (args[argidx] == "-noflatten") {
flatten = false;
continue;
@@ -326,7 +336,8 @@ struct SynthPass : public ScriptPass
if (check_label("map_gates")) {
run("opt -full");
- run("techmap -map +/techmap.v");
+ run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s",
+ help_mode ? "<carry>" : carry_mode.c_str()));
run("opt -fast");
}
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v
index 7ed6d83ff..12e01d2df 100644
--- a/techlibs/gatemate/cells_sim.v
+++ b/techlibs/gatemate/cells_sim.v
@@ -242,7 +242,8 @@ module CC_DFF #(
parameter [0:0] CLK_INV = 1'b0,
parameter [0:0] EN_INV = 1'b0,
parameter [0:0] SR_INV = 1'b0,
- parameter [0:0] SR_VAL = 1'b0
+ parameter [0:0] SR_VAL = 1'b0,
+ parameter [0:0] INIT = 1'bx
)(
input D,
(* clkbuf_sink *)
@@ -256,7 +257,7 @@ module CC_DFF #(
assign en = (EN_INV) ? ~EN : EN;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'bX;
+ initial Q = INIT;
always @(posedge clk or posedge sr)
begin
@@ -272,9 +273,10 @@ endmodule
module CC_DLT #(
- parameter [0:0] G_INV = 1'b0,
+ parameter [0:0] G_INV = 1'b0,
parameter [0:0] SR_INV = 1'b0,
- parameter [0:0] SR_VAL = 1'b0
+ parameter [0:0] SR_VAL = 1'b0,
+ parameter [0:0] INIT = 1'bx
)(
input D,
input G,
@@ -285,7 +287,7 @@ module CC_DLT #(
assign en = (G_INV) ? ~G : G;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'bX;
+ initial Q = INIT;
always @(*)
begin
diff --git a/techlibs/gatemate/reg_map.v b/techlibs/gatemate/reg_map.v
index 6a2c7fb91..6ec170a9d 100644
--- a/techlibs/gatemate/reg_map.v
+++ b/techlibs/gatemate/reg_map.v
@@ -21,25 +21,31 @@
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
- .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1")
+ .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
+ .INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
- .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
+ .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
+ .INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc
index dd4fde643..1d46d7929 100644
--- a/techlibs/gatemate/synth_gatemate.cc
+++ b/techlibs/gatemate/synth_gatemate.cc
@@ -283,7 +283,7 @@ struct SynthGateMatePass : public ScriptPass
if (check_label("map_regs"))
{
run("opt_clean");
- run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");
+ run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index ab8207ef1..535fd05ed 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -582,6 +582,14 @@ module IOBUF (O, IO, I, OEN);
assign I = IO;
endmodule
+module ELVDS_OBUF (I, O, OB);
+ input I;
+ output O;
+ output OB;
+ assign O = I;
+ assign OB = ~I;
+endmodule
+
module TLVDS_OBUF (I, O, OB);
input I;
output O;
@@ -1632,3 +1640,20 @@ output OSCOUT;
parameter FREQ_DIV = 96;
endmodule
+
+(* blackbox *)
+module OSCW(OSCOUT);
+output OSCOUT;
+
+parameter FREQ_DIV = 80;
+endmodule
+
+(* blackbox *)
+module OSCO(OSCOUT, OSCEN);
+input OSCEN;
+
+output OSCOUT;
+
+parameter FREQ_DIV = 100;
+parameter REGULATOR_EN = 1'b0;
+endmodule
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 52e8e2e3a..8943815bf 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1674,7 +1674,7 @@ module SB_RAM40_4K (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLK, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- (posedge RCLK => (RDATA : 16'bx)) = 2146;
+ (posedge RCLK *> (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
@@ -1696,7 +1696,7 @@ module SB_RAM40_4K (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLK, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- (posedge RCLK => (RDATA : 16'bx)) = 3163;
+ (posedge RCLK *> (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
@@ -1718,7 +1718,7 @@ module SB_RAM40_4K (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLK, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
- (posedge RCLK => (RDATA : 16'bx)) = 1179;
+ (posedge RCLK *> (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
@@ -1810,7 +1810,7 @@ module SB_RAM40_4KNR (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLK, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- (posedge RCLKN => (RDATA : 16'bx)) = 2146;
+ (posedge RCLKN *> (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
@@ -1832,7 +1832,7 @@ module SB_RAM40_4KNR (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLK, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- (posedge RCLKN => (RDATA : 16'bx)) = 3163;
+ (posedge RCLKN *> (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
@@ -1854,7 +1854,7 @@ module SB_RAM40_4KNR (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLK, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
- (posedge RCLKN => (RDATA : 16'bx)) = 1179;
+ (posedge RCLKN *> (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
@@ -1946,7 +1946,7 @@ module SB_RAM40_4KNW (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLKN, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- (posedge RCLK => (RDATA : 16'bx)) = 2146;
+ (posedge RCLK *> (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
@@ -1968,7 +1968,7 @@ module SB_RAM40_4KNW (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLKN, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- (posedge RCLK => (RDATA : 16'bx)) = 3163;
+ (posedge RCLK *> (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
@@ -1990,7 +1990,7 @@ module SB_RAM40_4KNW (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLKN, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
- (posedge RCLK => (RDATA : 16'bx)) = 1179;
+ (posedge RCLK *> (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
@@ -2082,7 +2082,7 @@ module SB_RAM40_4KNRNW (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLKN, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- (posedge RCLKN => (RDATA : 16'bx)) = 2146;
+ (posedge RCLKN *> (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
@@ -2104,7 +2104,7 @@ module SB_RAM40_4KNRNW (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLKN, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- (posedge RCLKN => (RDATA : 16'bx)) = 3163;
+ (posedge RCLKN *> (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
@@ -2126,7 +2126,7 @@ module SB_RAM40_4KNRNW (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLKN, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
- (posedge RCLKN => (RDATA : 16'bx)) = 1179;
+ (posedge RCLKN *> (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
@@ -2653,9 +2653,9 @@ module SB_SPRAM256KA (
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
$setup(WREN, posedge CLOCK, 289);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
- (posedge CLOCK => (DATAOUT : 16'bx)) = 1821;
+ (posedge CLOCK *> (DATAOUT : 16'bx)) = 1821;
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
- (posedge SLEEP => (DATAOUT : 16'b0)) = 1099;
+ (posedge SLEEP *> (DATAOUT : 16'b0)) = 1099;
endspecify
`endif
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 18:16:06 +0000