diff options
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/Makefile.inc | 2 | ||||
| -rw-r--r-- | techlibs/simlib.v | 9 |
2 files changed, 5 insertions, 6 deletions
diff --git a/techlibs/Makefile.inc b/techlibs/Makefile.inc index 031a4ad30..6c2a5f66a 100644 --- a/techlibs/Makefile.inc +++ b/techlibs/Makefile.inc @@ -1,5 +1,5 @@ -TARGETS += techlibs/blackbox.v +EXTRA_TARGETS += techlibs/blackbox.v techlibs/blackbox.v: techlibs/blackbox.sed techlibs/simlib.v techlibs/stdcells_sim.v cat techlibs/simlib.v techlibs/stdcells_sim.v | sed -rf techlibs/blackbox.sed > techlibs/blackbox.v.new diff --git a/techlibs/simlib.v b/techlibs/simlib.v index 29c13503b..ff988cbe5 100644 --- a/techlibs/simlib.v +++ b/techlibs/simlib.v @@ -646,7 +646,6 @@ module \$sr (S, R, Q); parameter WIDTH = 0; -input CLK; input [WIDTH-1:0] S, R; output reg [WIDTH-1:0] Q; @@ -800,8 +799,8 @@ parameter MEMID = ""; parameter ABITS = 8; parameter WIDTH = 8; -parameter RD_CLK_ENABLE = 0; -parameter RD_CLK_POLARITY = 0; +parameter CLK_ENABLE = 0; +parameter CLK_POLARITY = 0; input CLK; input [ABITS-1:0] ADDR; @@ -822,8 +821,8 @@ parameter MEMID = ""; parameter ABITS = 8; parameter WIDTH = 8; -parameter RD_CLK_ENABLE = 0; -parameter RD_CLK_POLARITY = 0; +parameter CLK_ENABLE = 0; +parameter CLK_POLARITY = 0; input CLK, EN; input [ABITS-1:0] ADDR; |