diff options
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/ecp5_gsr.cc | 2 | ||||
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 10 | ||||
| -rw-r--r-- | techlibs/xilinx/xilinx_dffopt.cc | 9 |
3 files changed, 17 insertions, 4 deletions
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index 1c69e1d79..3d3f8e1c1 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -81,7 +81,7 @@ struct Ecp5GsrPass : public Pass { for (auto cell : module->selected_cells()) { - if (cell->getParam(ID(GSR)).decode_string() != "AUTO") + if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") continue; bool gsren = found_gsr; diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 47aa11500..5d4c78d74 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -200,6 +200,8 @@ struct SynthIntelALMPass : public ScriptPass { if (check_label("map_ffs")) { run("dff2dffe -direct-match $_DFF_*"); + // As mentioned in common/dff_sim.v, Intel flops power up to zero, + // so use `zinit` to add inverters where needed. run("zinit"); run("techmap -map +/techmap.v -map +/intel_alm/common/dff_map.v"); run("opt -full -undriven -mux_undef"); @@ -223,8 +225,16 @@ struct SynthIntelALMPass : public ScriptPass { if (check_label("quartus")) { if (quartus || help_mode) { + // Quartus ICEs if you have a wire which has `[]` in its name, + // which Yosys produces when building memories out of flops. + run("rename -hide w:*[* w:*]*"); + // VQM mode does not support 'x, so replace those with zero. run("setundef -zero"); + // VQM mode does not support multi-bit constant assignments + // (e.g. 2'b00 is an error), so as a workaround use references + // to constant driver cells, which Quartus accepts. run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q"); + // Rename from Yosys-internal MISTRAL_* cells to Quartus cells. run("techmap -map +/intel_alm/common/quartus_rename.v"); run(stringf("techmap -map +/intel_alm/%s/quartus_rename.v", family_opt.c_str())); } diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index c608db883..c9d63c9f7 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -292,18 +292,21 @@ unmap: LutData final_lut; if (worthy_post_r) { final_lut = lut_d_post_r; - log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else if (worthy_post_s) { final_lut = lut_d_post_s; - log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else if (worthy_post_ce) { final_lut = lut_d_post_ce; - log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else { // Nothing to do here. continue; } + std::string ports; + if (worthy_post_r) ports += " + R"; + if (worthy_post_s) ports += " + S"; + if (worthy_post_ce) ports += " + CE"; + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + // Okay, we're doing it. Unmap ports. if (worthy_post_r) { cell->unsetParam(ID(IS_R_INVERTED)); |