diff options
Diffstat (limited to 'techlibs')
36 files changed, 2206 insertions, 93 deletions
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index 6c87adb94..fc15e0966 100644 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -68,9 +68,8 @@ end assign dout = combout_rt & 1'b1; endmodule -module DFF (output q, +module DFF (output reg q, input d, ck); - reg q; always @(posedge ck) q <= d; diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 607e772a2..47f1ed604 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -22,6 +22,7 @@ kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help $(eval $(call add_share_file,share,techlibs/common/simlib.v)) $(eval $(call add_share_file,share,techlibs/common/simcells.v)) $(eval $(call add_share_file,share,techlibs/common/techmap.v)) +$(eval $(call add_share_file,share,techlibs/common/smtmap.v)) $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v)) $(eval $(call add_share_file,share,techlibs/common/adff2dff.v)) $(eval $(call add_share_file,share,techlibs/common/dff2ff.v)) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b14488ff4..9cb68e725 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1279,14 +1279,9 @@ parameter WIDTH = 0; input [WIDTH-1:0] A, B; input S; -output reg [WIDTH-1:0] Y; +output [WIDTH-1:0] Y; -always @* begin - if (S) - Y = B; - else - Y = A; -end +assign Y = S ? B : A; endmodule @@ -1305,11 +1300,11 @@ wire [WIDTH-1:0] bm0_out, bm1_out; generate if (S_WIDTH > 1) begin:muxlogic - \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); + \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out)); assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out; end else if (S_WIDTH == 1) begin:simple - assign Y = S ? A[1] : A[0]; + assign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0]; end else begin:passthru assign Y = A; end @@ -1336,10 +1331,17 @@ always @* begin Y = A; found_active_sel_bit = 0; for (i = 0; i < S_WIDTH; i = i+1) - if (S[i]) begin - Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i); - found_active_sel_bit = 1; - end + case (S[i]) + 1'b1: begin + Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i); + found_active_sel_bit = 1; + end + 1'b0: ; + 1'bx: begin + Y = 'bx; + found_active_sel_bit = 'bx; + end + endcase end endmodule @@ -1375,7 +1377,7 @@ parameter LUT = 0; input [WIDTH-1:0] A; output Y; -\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT), .S(A), .Y(Y)); +\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y)); endmodule @@ -1599,6 +1601,43 @@ endmodule // -------------------------------------------------------- +module \$bweqx (A, B, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A, B; +output [WIDTH-1:0] Y; + +genvar i; +generate + for (i = 0; i < WIDTH; i = i + 1) begin:slices + assign Y[i] = A[i] === B[i]; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + +module \$bwmux (A, B, S, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A, B; +input [WIDTH-1:0] S; +output [WIDTH-1:0] Y; + +genvar i; +generate + for (i = 0; i < WIDTH; i = i + 1) begin:slices + assign Y[i] = S[i] ? B[i] : A[i]; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + module \$assert (A, EN); input A, EN; @@ -1697,6 +1736,26 @@ assign Y = 'bx; endmodule // -------------------------------------------------------- +`ifdef SIMLIB_FF +`ifndef SIMLIB_GLOBAL_CLOCK +`define SIMLIB_GLOBAL_CLOCK $global_clk +`endif +module \$anyinit (D, Q); + +parameter WIDTH = 0; + +input [WIDTH-1:0] D; +output reg [WIDTH-1:0] Q; + +initial Q <= 'bx; + +always @(`SIMLIB_GLOBAL_CLOCK) begin + Q <= D; +end + +endmodule +`endif +// -------------------------------------------------------- module \$allconst (Y); @@ -1771,6 +1830,9 @@ endmodule `endif // -------------------------------------------------------- `ifdef SIMLIB_FF +`ifndef SIMLIB_GLOBAL_CLOCK +`define SIMLIB_GLOBAL_CLOCK $global_clk +`endif module \$ff (D, Q); @@ -1779,7 +1841,7 @@ parameter WIDTH = 0; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; -always @($global_clk) begin +always @(`SIMLIB_GLOBAL_CLOCK) begin Q <= D; end diff --git a/techlibs/common/smtmap.v b/techlibs/common/smtmap.v new file mode 100644 index 000000000..8c7503dc8 --- /dev/null +++ b/techlibs/common/smtmap.v @@ -0,0 +1,28 @@ +(* techmap_celltype = "$pmux" *) +module smt_pmux (A, B, S, Y); + parameter WIDTH = 1; + parameter S_WIDTH = 1; + + (* force_downto *) + input [WIDTH-1:0] A; + (* force_downto *) + input [WIDTH*S_WIDTH-1:0] B; + (* force_downto *) + input [S_WIDTH-1:0] S; + (* force_downto *) + output [WIDTH-1:0] Y; + + (* force_downto *) + wire [WIDTH-1:0] Y_B; + + genvar i, j; + generate + (* force_downto *) + wire [WIDTH*(S_WIDTH+1)-1:0] C; + + assign C[WIDTH-1:0] = A; + for (i = 0; i < S_WIDTH; i = i + 1) + assign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i]; + assign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH]; + endgenerate +endmodule diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 91d385b80..7fb8173b0 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -59,7 +59,7 @@ module _90_simplemap_compare_ops; endmodule (* techmap_simplemap *) -(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux" *) +(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *) module _90_simplemap_various; endmodule diff --git a/techlibs/fabulous/Makefile.inc b/techlibs/fabulous/Makefile.inc new file mode 100644 index 000000000..44d57542b --- /dev/null +++ b/techlibs/fabulous/Makefile.inc @@ -0,0 +1,10 @@ + +OBJS += techlibs/fabulous/synth_fabulous.o + +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/cells_map.v)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/prims.v)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/latches_map.v)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v)) diff --git a/techlibs/fabulous/cells_map.v b/techlibs/fabulous/cells_map.v new file mode 100644 index 000000000..eadd18b6f --- /dev/null +++ b/techlibs/fabulous/cells_map.v @@ -0,0 +1,29 @@ +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0])); + + end else + if (WIDTH == 2) begin + LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1])); + + end else + if (WIDTH == 3) begin + LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); + + end else + if (WIDTH == 4) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule + +module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule diff --git a/techlibs/fabulous/ff_map.v b/techlibs/fabulous/ff_map.v new file mode 100644 index 000000000..0a03bd692 --- /dev/null +++ b/techlibs/fabulous/ff_map.v @@ -0,0 +1,9 @@ +module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule + +module \$_DFFE_PP_ (input D, C, E, output Q); LUTFF_E _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E)); endmodule + +module \$_SDFF_PP0_ (input D, C, R, output Q); LUTFF_SR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .R(R)); endmodule +module \$_SDFF_PP1_ (input D, C, R, output Q); LUTFF_SS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .S(R)); endmodule + +module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); LUTFF_ESR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .R(R)); endmodule +module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); LUTFF_ESS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .S(R)); endmodule diff --git a/techlibs/fabulous/io_map.v b/techlibs/fabulous/io_map.v new file mode 100644 index 000000000..c1d4160f8 --- /dev/null +++ b/techlibs/fabulous/io_map.v @@ -0,0 +1,8 @@ +module \$__FABULOUS_IBUF (input PAD, output O); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .O(O), .T(1'b1)); +endmodule + +module \$__FABULOUS_OBUF (output PAD, input I); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0)); +endmodule + diff --git a/techlibs/fabulous/latches_map.v b/techlibs/fabulous/latches_map.v new file mode 100644 index 000000000..c28f88cf7 --- /dev/null +++ b/techlibs/fabulous/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v new file mode 100644 index 000000000..8ddae5beb --- /dev/null +++ b/techlibs/fabulous/prims.v @@ -0,0 +1,417 @@ +module LUT1(output O, input I0); + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; +endmodule + +module LUT2(output O, input I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT3(output O, input I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT4(output O, input I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUTFF(input CLK, D, output reg O); + initial O = 1'b0; + always @ (posedge CLK) begin + O <= D; + end +endmodule + +module FABULOUS_MUX2(input I0, I1, S0, output O); + assign O = S0 ? I1 : I0; +endmodule + +module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O); + wire A0 = S0 ? I1 : I0; + wire A1 = S0 ? I3 : I2; + assign O = S1 ? A1 : A0; +endmodule + +module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O); + wire A0 = S0 ? I1 : I0; + wire A1 = S0 ? I3 : I2; + wire A2 = S0 ? I5 : I4; + wire A3 = S0 ? I7 : I6; + wire B0 = S1 ? A1 : A0; + wire B1 = S1 ? A3 : A2; + assign O = S2 ? B1 : B0; +endmodule + +module FABULOUS_LC #( + parameter K = 4, + parameter [2**K-1:0] INIT = 0, + parameter DFF_ENABLE = 1'b0 +) ( + input CLK, + input [K-1:0] I, + output O, + output Q +); + wire f_wire; + + //LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); + generate + if (K == 1) begin + LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0])); + end else + if (K == 2) begin + LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1])); + end else + if (K == 3) begin + LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2])); + end else + if (K == 4) begin + LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3])); + end + endgenerate + + LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); + + assign O = f_wire; +endmodule + +(* blackbox *) +module Global_Clock (output CLK); +`ifndef SYNTHESIS + initial CLK = 0; + always #10 CLK = ~CLK; +`endif +endmodule + +(* blackbox, keep *) +module InPass4_frame_config (output O0, O1, O2, O3); + +endmodule + + +(* blackbox, keep *) +module OutPass4_frame_config (input I0, I1, I2, I3); + +endmodule + +(* keep *) +module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD); + assign PAD = T ? 1'bz : I; + assign O = PAD; + reg Q_q; + always @(posedge CLK) Q_q <= O; + assign Q = Q_q; +endmodule + + +module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK); + parameter A_reg = 1'b0; + parameter B_reg = 1'b0; + parameter C_reg = 1'b0; + parameter ACC = 1'b0; + parameter signExtension = 1'b0; + parameter ACCout = 1'b0; + + //parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value) + // IMPORTANT: this has to be in a dedicated line + input A7;// operand A + input A6; + input A5; + input A4; + input A3; + input A2; + input A1; + input A0; + input B7;// operand B + input B6; + input B5; + input B4; + input B3; + input B2; + input B1; + input B0; + input C19;// operand C + input C18; + input C17; + input C16; + input C15; + input C14; + input C13; + input C12; + input C11; + input C10; + input C9; + input C8; + input C7; + input C6; + input C5; + input C4; + input C3; + input C2; + input C1; + input C0; + output Q19;// result + output Q18; + output Q17; + output Q16; + output Q15; + output Q14; + output Q13; + output Q12; + output Q11; + output Q10; + output Q9; + output Q8; + output Q7; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; + + input clr; + input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) + // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label + + + wire [7:0] A; // port A read data + wire [7:0] B; // port B read data + wire [19:0] C; // port B read data + reg [7:0] A_q; // port A read data register + reg [7:0] B_q; // port B read data register + reg [19:0] C_q; // port B read data register + wire [7:0] OPA; // port A + wire [7:0] OPB; // port B + wire [19:0] OPC; // port B + reg [19:0] ACC_data ; // accumulator register + wire [19:0] sum;// port B read data register + wire [19:0] sum_in;// port B read data register + wire [15:0] product; + wire [19:0] product_extended; + + assign A = {A7,A6,A5,A4,A3,A2,A1,A0}; + assign B = {B7,B6,B5,B4,B3,B2,B1,B0}; + assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0}; + + assign OPA = A_reg ? A_q : A; + assign OPB = B_reg ? B_q : B; + assign OPC = C_reg ? C_q : C; + + assign sum_in = ACC ? ACC_data : OPC;// we can + + assign product = OPA * OPB; + +// The sign extension was not tested + assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product}; + + assign sum = product_extended + sum_in; + + assign Q19 = ACCout ? ACC_data[19] : sum[19]; + assign Q18 = ACCout ? ACC_data[18] : sum[18]; + assign Q17 = ACCout ? ACC_data[17] : sum[17]; + assign Q16 = ACCout ? ACC_data[16] : sum[16]; + assign Q15 = ACCout ? ACC_data[15] : sum[15]; + assign Q14 = ACCout ? ACC_data[14] : sum[14]; + assign Q13 = ACCout ? ACC_data[13] : sum[13]; + assign Q12 = ACCout ? ACC_data[12] : sum[12]; + assign Q11 = ACCout ? ACC_data[11] : sum[11]; + assign Q10 = ACCout ? ACC_data[10] : sum[10]; + assign Q9 = ACCout ? ACC_data[9] : sum[9]; + assign Q8 = ACCout ? ACC_data[8] : sum[8]; + assign Q7 = ACCout ? ACC_data[7] : sum[7]; + assign Q6 = ACCout ? ACC_data[6] : sum[6]; + assign Q5 = ACCout ? ACC_data[5] : sum[5]; + assign Q4 = ACCout ? ACC_data[4] : sum[4]; + assign Q3 = ACCout ? ACC_data[3] : sum[3]; + assign Q2 = ACCout ? ACC_data[2] : sum[2]; + assign Q1 = ACCout ? ACC_data[1] : sum[1]; + assign Q0 = ACCout ? ACC_data[0] : sum[0]; + + always @ (posedge CLK) + begin + A_q <= A; + B_q <= B; + C_q <= C; + if (clr == 1'b1) begin + ACC_data <= 20'b00000000000000000000; + end else begin + ACC_data <= sum; + end + end + +endmodule + +module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK); + //parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value) + parameter AD_reg = 1'b0; + parameter BD_reg = 1'b0; + // IMPORTANT: this has to be in a dedicated line + input D0; // Register File write port + input D1; + input D2; + input D3; + input W_ADR0; + input W_ADR1; + input W_ADR2; + input W_ADR3; + input W_ADR4; + input W_en; + + output AD0;// Register File read port A + output AD1; + output AD2; + output AD3; + input A_ADR0; + input A_ADR1; + input A_ADR2; + input A_ADR3; + input A_ADR4; + + output BD0;//Register File read port B + output BD1; + output BD2; + output BD3; + input B_ADR0; + input B_ADR1; + input B_ADR2; + input B_ADR3; + input B_ADR4; + + input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) + + // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label + + + //type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit + //signal mem : memtype := (others => (others => '0')); + reg [3:0] mem [31:0]; + + wire [4:0] W_ADR;// write address + wire [4:0] A_ADR;// port A read address + wire [4:0] B_ADR;// port B read address + + wire [3:0] D; // write data + wire [3:0] AD; // port A read data + wire [3:0] BD; // port B read data + + reg [3:0] AD_q; // port A read data register + reg [3:0] BD_q; // port B read data register + + integer i; + + assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0}; + assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0}; + assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0}; + + assign D = {D3,D2,D1,D0}; + + initial begin + for (i=0; i<32; i=i+1) begin + mem[i] = 4'b0000; + end + end + + always @ (posedge CLK) begin : P_write + if (W_en == 1'b1) begin + mem[W_ADR] <= D ; + end + end + + assign AD = mem[A_ADR]; + assign BD = mem[B_ADR]; + + always @ (posedge CLK) begin + AD_q <= AD; + BD_q <= BD; + end + + assign AD0 = AD_reg ? AD_q[0] : AD[0]; + assign AD1 = AD_reg ? AD_q[1] : AD[1]; + assign AD2 = AD_reg ? AD_q[2] : AD[2]; + assign AD3 = AD_reg ? AD_q[3] : AD[3]; + + assign BD0 = BD_reg ? BD_q[0] : BD[0]; + assign BD1 = BD_reg ? BD_q[1] : BD[1]; + assign BD2 = BD_reg ? BD_q[2] : BD[2]; + assign BD3 = BD_reg ? BD_q[3] : BD[3]; + +endmodule + +`ifdef EQUIV +`define COMPLEX_DFF +`endif + +`ifdef COMPLEX_DFF +module LUTFF_E ( + output reg O, + input CLK, E, D +); + initial O = 1'b0; + always @(posedge CLK) + if (E) + O <= D; +endmodule + +module LUTFF_SR ( + output reg O, + input CLK, R, D +); + initial O = 1'b0; + always @(posedge CLK) + if (R) + O <= 0; + else + O <= D; +endmodule + +module LUTFF_SS ( + output reg O, + input CLK, S, D +); + initial O = 1'b0; + always @(posedge CLK) + if (S) + O <= 1; + else + O <= D; +endmodule + +module LUTFF_ESR ( + output reg O, + input CLK, E, R, D +); + initial O = 1'b0; + always @(posedge CLK) + if (E) begin + if (R) + O <= 0; + else + O <= D; + end +endmodule + +module LUTFF_ESS ( + output reg O, + input CLK, E, S, D +); + initial O = 1'b0; + always @(posedge CLK) + if (E) begin + if (S) + O <= 1; + else + O <= D; + end +endmodule +`endif // COMPLEX_DFF
\ No newline at end of file diff --git a/techlibs/fabulous/ram_regfile.txt b/techlibs/fabulous/ram_regfile.txt new file mode 100644 index 000000000..af834b005 --- /dev/null +++ b/techlibs/fabulous/ram_regfile.txt @@ -0,0 +1,46 @@ +# Yosys doesn't support configurable sync/async ports. +# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync + +ram distributed $__REGFILE_AA_ { + abits 5; + width 4; + cost 6; + port sw "W" { + clock posedge "CLK"; + } + port ar "A" { + } + port ar "B" { + } +} + +ram distributed $__REGFILE_SA_ { + abits 5; + width 4; + cost 5; + port sw "W" { + clock posedge "CLK"; + wrtrans all old; + } + port sr "A" { + clock posedge "CLK"; + } + port ar "B" { + } +} + +ram distributed $__REGFILE_SS_ { + abits 5; + width 4; + cost 4; + port sw "W" { + clock posedge "CLK"; + wrtrans all old; + } + port sr "A" { + clock posedge "CLK"; + } + port sr "B" { + clock posedge "CLK"; + } +} diff --git a/techlibs/fabulous/regfile_map.v b/techlibs/fabulous/regfile_map.v new file mode 100644 index 000000000..14342495e --- /dev/null +++ b/techlibs/fabulous/regfile_map.v @@ -0,0 +1,42 @@ +(* techmap_celltype = "$__REGFILE_[AS][AS]_" *) +module \$__REGFILE_XX_ (...); + +parameter _TECHMAP_CELLTYPE_ = ""; +localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S"; +localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S"; + +localparam WIDTH = 4; +localparam ABITS = 5; + +input [WIDTH-1:0] PORT_W_WR_DATA; +input [ABITS-1:0] PORT_W_ADDR; +input PORT_W_WR_EN; + +output [WIDTH-1:0] PORT_A_RD_DATA; +input [ABITS-1:0] PORT_A_ADDR; + +output [WIDTH-1:0] PORT_B_RD_DATA; +input [ABITS-1:0] PORT_B_ADDR; + +// Unused - we have a shared clock - but keep techmap happy +input PORT_W_CLK; +input PORT_A_CLK; +input PORT_B_CLK; + +input CLK_CLK; + +RegFile_32x4 #( + .AD_reg(A_SYNC), + .BD_reg(B_SYNC) +) _TECHMAP_REPLACE_ ( + .D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]), + .W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]), + .W_en(PORT_W_WR_EN), + .AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]), + .A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]), + .BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]), + .B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]), + .CLK(CLK_CLK) +); + +endmodule diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc new file mode 100644 index 000000000..d7c45e094 --- /dev/null +++ b/techlibs/fabulous/synth_fabulous.cc @@ -0,0 +1,396 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthPass : public ScriptPass +{ + SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") { } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_fabulous [options]\n"); + log("\n"); + log("This command runs synthesis for FPGA fabrics generated with FABulous. This command does not operate\n"); + log("on partly selected designs.\n"); + log("\n"); + log(" -top <module>\n"); + log(" use the specified module as top module (default='top')\n"); + log("\n"); + log(" -auto-top\n"); + log(" automatically determine the top of the design hierarchy\n"); + log("\n"); + log(" -blif <file>\n"); + log(" write the design to the specified BLIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -edif <file>\n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json <file>\n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -lut <k>\n"); + log(" perform synthesis for a k-LUT architecture (default 4).\n"); + log("\n"); + log(" -vpr\n"); + log(" perform synthesis for the FABulous VPR flow (using slightly different techmapping).\n"); + log("\n"); + log(" -plib <primitive_library.v>\n"); + log(" use the specified Verilog file as a primitive library.\n"); + log("\n"); + log(" -extra-plib <primitive_library.v>\n"); + log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); + log(" times).\n"); + log("\n"); + log(" -extra-map <techamp.v>\n"); + log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); + log(" times).\n"); + log("\n"); + log(" -encfile <file>\n"); + log(" passed to 'fsm_recode' via 'fsm'\n"); + log("\n"); + log(" -nofsm\n"); + log(" do not run FSM optimization\n"); + log("\n"); + log(" -noalumacc\n"); + log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n"); + log(" their direct form ($add, $sub, etc.).\n"); + log("\n"); + log(" -noregfile\n"); + log(" do not map register files\n"); + log("\n"); + log(" -iopad\n"); + log(" enable automatic insertion of IO buffers (otherwise a wrapper\n"); + log(" with manually inserted and constrained IO should be used.)\n"); + log("\n"); + log(" -complex-dff\n"); + log(" enable support for FFs with enable and synchronous SR (must also be\n"); + log(" supported by the target fabric.)\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design after elaboration\n"); + log("\n"); + log(" -nordff\n"); + log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n"); + log("\n"); + log(" -noshare\n"); + log(" do not run SAT-based resource sharing\n"); + log("\n"); + log(" -run <from_label>[:<to_label>]\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_module, json_file, blif_file, plib, fsm_opts, memory_opts; + std::vector<string> extra_plib, extra_map; + + bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; + int lut; + + void clear_flags() override + { + top_module.clear(); + plib.clear(); + autotop = false; + lut = 4; + forvpr = false; + noalumacc = false; + nofsm = false; + noshare = false; + iopad = false; + complexdff = false; + flatten = true; + json_file = ""; + blif_file = ""; + } + + void execute(std::vector<std::string> args, RTLIL::Design *design) override + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_module = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-blif" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) { + run_from = args[++argidx]; + run_to = args[argidx]; + } else { + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + } + continue; + } + if (args[argidx] == "-vpr") { + forvpr = true; + continue; + } + if (args[argidx] == "-auto-top") { + autotop = true; + continue; + } + if (args[argidx] == "-lut") { + lut = atoi(args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-plib" && argidx+1 < args.size()) { + plib = args[++argidx]; + continue; + } + if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) { + extra_plib.push_back(args[++argidx]); + continue; + } + if (args[argidx] == "-extra-map" && argidx+1 < args.size()) { + extra_map.push_back(args[++argidx]); + continue; + } + if (args[argidx] == "-nofsm") { + nofsm = true; + continue; + } + if (args[argidx] == "-noalumacc") { + noalumacc = true; + continue; + } + if (args[argidx] == "-nordff") { + memory_opts += " -nordff"; + continue; + } + if (args[argidx] == "-noshare") { + noshare = true; + continue; + } + if (args[argidx] == "-no-rw-check") { + memory_opts += " -no-rw-check"; + continue; + } + if (args[argidx] == "-noregfile") { + noregfile = true; + continue; + } + if (args[argidx] == "-iopad") { + iopad = true; + continue; + } + if (args[argidx] == "-complex-dff") { + complexdff = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_FABULOUS pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + if (plib.empty()) + run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : "")); + else + run("read_verilog -lib " + plib); + + if (help_mode) { + run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)"); + } else for (auto lib : extra_plib) { + run("read_verilog -lib " + lib); + } + + if (check_label("begin")) { + if (top_module.empty()) { + if (autotop) + run("hierarchy -check -auto-top"); + else + run("hierarchy -check"); + } else + run(stringf("hierarchy -check -top %s", top_module.c_str())); + run("proc"); + } + + + if (check_label("flatten", "(unless -noflatten)")) + { + if (flatten) { + run("flatten"); + run("tribuf -logic"); + run("deminout"); + } + } + + if (check_label("coarse")) { + run("tribuf -logic"); + run("deminout"); + + // synth pass + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + if (!nofsm) + run("fsm" + fsm_opts, " (unless -nofsm)"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + if (help_mode) + run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); + else if (lut) + run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + if (!noalumacc) + run("alumacc", " (unless -noalumacc)"); + if (!noshare) + run("share", " (unless -noshare)"); + run("opt"); + run("memory -nomap" + memory_opts); + run("opt_clean"); + } + + if (check_label("map_ram")) { + // RegFile extraction + if (!noregfile) { + run("memory_libmap -lib +/fabulous/ram_regfile.txt"); + run("techmap -map +/fabulous/regfile_map.v"); + } + } + + if (check_label("map_ffram")) { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + } + + if (check_label("map_gates")) { + run("opt -full"); + run("techmap -map +/techmap.v"); + run("opt -fast"); + } + + if (check_label("map_iopad", "(if -iopad)")) { + if (iopad) { + run("opt -full"); + run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD " + "-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD " + "-tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top", "(skip if '-noiopad')"); + run("techmap -map +/fabulous/io_map.v"); + } + } + + + if (check_label("map_ffs")) { + if (complexdff) { + run("dfflegalize -cell $_DFF_P_ 0 -cell $_SDFF_PP?_ 0 -cell $_SDFFCE_PP?P_ 0 -cell $_DLATCH_?_ x", "with -complex-dff"); + } else { + run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff"); + } + run("techmap -map +/fabulous/latches_map.v"); + run("techmap -map +/fabulous/ff_map.v"); + if (help_mode) { + run("techmap -map <extra_map.v>...", "(for each -extra-map)"); + } else if (!extra_map.empty()) { + std::string map_str = "techmap"; + for (auto map : extra_map) + map_str += stringf(" -map %s", map.c_str()); + run(map_str); + } + run("clean"); + } + + if (check_label("map_luts")) { + run(stringf("abc -lut %d -dress", lut)); + run("clean"); + } + + if (check_label("map_cells")) { + if (!forvpr) + run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut)); + run("clean"); + } + if (check_label("check")) { + run("hierarchy -check"); + run("stat"); + } + + if (check_label("blif")) + { + if (!blif_file.empty() || help_mode) + { + run("opt_clean -purge"); + run(stringf("write_blif -attr -cname -conn -param %s", + help_mode ? "<file-name>" : blif_file.c_str())); + } + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str())); + } + } +} SynthPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/gatemate/.gitignore b/techlibs/gatemate/.gitignore new file mode 100644 index 000000000..f260d6e9d --- /dev/null +++ b/techlibs/gatemate/.gitignore @@ -0,0 +1,4 @@ +lut_tree_cells.genlib +lut_tree_map.v +lut_tree_lib.mk + diff --git a/techlibs/gatemate/Makefile.inc b/techlibs/gatemate/Makefile.inc index d1341d7bb..aeb318cc9 100644 --- a/techlibs/gatemate/Makefile.inc +++ b/techlibs/gatemate/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/gatemate/synth_gatemate.o
+OBJS += techlibs/gatemate/gatemate_foldinv.o
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/reg_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mux_map.v))
@@ -12,3 +13,18 @@ $(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_map.v)) $(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams.txt))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_20.vh))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_40.vh))
+$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/inv_map.v))
+
+EXTRA_OBJS += techlibs/gatemate/lut_tree_lib.mk
+.SECONDARY: techlibs/gatemate/lut_tree_lib.mk
+
+techlibs/gatemate/lut_tree_lib.mk: techlibs/gatemate/make_lut_tree_lib.py
+ $(Q) mkdir -p techlibs/gatemate
+ $(P) $(PYTHON_EXECUTABLE) $<
+ $(Q) touch $@
+
+techlibs/gatemate/lut_tree_cells.genlib: techlibs/gatemate/lut_tree_lib.mk
+techlibs/gatemate/lut_tree_map.v: techlibs/gatemate/lut_tree_lib.mk
+
+$(eval $(call add_gen_share_file,share/gatemate,techlibs/gatemate/lut_tree_cells.genlib))
+$(eval $(call add_gen_share_file,share/gatemate,techlibs/gatemate/lut_tree_map.v))
diff --git a/techlibs/gatemate/cells_bb.v b/techlibs/gatemate/cells_bb.v index f6fe6a3e1..87b91764f 100644 --- a/techlibs/gatemate/cells_bb.v +++ b/techlibs/gatemate/cells_bb.v @@ -22,6 +22,9 @@ module CC_PLL #( parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
+ parameter LOCK_REQ = 1,
+ parameter CLK270_DOUB = 0,
+ parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
@@ -123,6 +126,12 @@ module CC_CFG_CTRL( );
endmodule
+(* blackbox *) (* keep *)
+module CC_USR_RSTN (
+ output USR_RSTN
+);
+endmodule
+
(* blackbox *)
module CC_FIFO_40K (
output A_ECC_1B_ERR,
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 1de3d1c7a..7ed6d83ff 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -114,10 +114,10 @@ module CC_LVDS_IBUF #( parameter [0:0] FF_IBF = 1'bx
)(
(* iopad_external_pin *)
- input IP, IN,
+ input I_P, I_N,
output Y
);
- assign Y = IP;
+ assign Y = I_P;
endmodule
@@ -133,10 +133,10 @@ module CC_LVDS_OBUF #( )(
input A,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = A;
- assign ON = ~A;
+ assign O_P = A;
+ assign O_N = ~A;
endmodule
@@ -152,10 +152,10 @@ module CC_LVDS_TOBUF #( )(
input A, T,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = T ? 1'bz : A;
- assign ON = T ? 1'bz : ~A;
+ assign O_P = T ? 1'bz : A;
+ assign O_N = T ? 1'bz : ~A;
endmodule
@@ -174,12 +174,12 @@ module CC_LVDS_IOBUF #( )(
input A, T,
(* iopad_external_pin *)
- inout IOP, ION,
+ inout IO_P, IO_N,
output Y
);
- assign IOP = T ? 1'bz : A;
- assign ION = T ? 1'bz : ~A;
- assign Y = IOP;
+ assign IO_P = T ? 1'bz : A;
+ assign IO_N = T ? 1'bz : ~A;
+ assign Y = IO_P;
endmodule
@@ -1409,3 +1409,47 @@ module CC_BRAM_40K ( end
endgenerate
endmodule
+
+// Models of the LUT2 tree primitives
+module CC_L2T4(
+ output O,
+ input I0, I1, I2, I3
+);
+ parameter [3:0] INIT_L00 = 4'b0000;
+ parameter [3:0] INIT_L01 = 4'b0000;
+ parameter [3:0] INIT_L10 = 4'b0000;
+
+ wire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0];
+ wire l00 = I0 ? l00_s1[1] : l00_s1[0];
+
+ wire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0];
+ wire l01 = I2 ? l01_s1[1] : l01_s1[0];
+
+ wire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0];
+ assign O = l00 ? l10_s1[1] : l10_s1[0];
+
+endmodule
+
+
+module CC_L2T5(
+ output O,
+ input I0, I1, I2, I3, I4
+);
+ parameter [3:0] INIT_L02 = 4'b0000;
+ parameter [3:0] INIT_L03 = 4'b0000;
+ parameter [3:0] INIT_L11 = 4'b0000;
+ parameter [3:0] INIT_L20 = 4'b0000;
+
+ wire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0];
+ wire l02 = I0 ? l02_s1[1] : l02_s1[0];
+
+ wire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0];
+ wire l03 = I2 ? l03_s1[1] : l03_s1[0];
+
+ wire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0];
+ wire l11 = l02 ? l11_s1[1] : l11_s1[0];
+
+ wire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0];
+ assign O = I4 ? l20_s1[1] : l20_s1[0];
+
+endmodule
diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc new file mode 100644 index 000000000..752f8aac0 --- /dev/null +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -0,0 +1,219 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 gatecat <gatecat@ds0.me> + * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct LUTPin { + int input_bit; + IdString init_param; +}; + +struct LUTType { + dict<IdString, LUTPin> inputs; + IdString output_param; +}; + +struct FoldInvWorker { + FoldInvWorker(Module *module) : module(module), sigmap(module) {}; + Module *module; + SigMap sigmap; + + // Mapping from inverter output to inverter input + dict<SigBit, SigBit> inverted_bits; + // Mapping from inverter input to inverter + dict<SigBit, Cell*> inverter_input; + + const dict<IdString, LUTType> lut_types = { + {ID(CC_LUT2), {{ + {ID(I0), {0, ID(INIT)}}, + {ID(I1), {1, ID(INIT)}}, + }, ID(INIT)}}, + {ID(CC_L2T4), {{ + {ID(I0), {0, ID(INIT_L00)}}, + {ID(I1), {1, ID(INIT_L00)}}, + {ID(I2), {0, ID(INIT_L01)}}, + {ID(I3), {1, ID(INIT_L01)}}, + }, ID(INIT_L10)}}, + {ID(CC_L2T5), {{ + {ID(I0), {0, ID(INIT_L02)}}, + {ID(I1), {1, ID(INIT_L02)}}, + {ID(I2), {0, ID(INIT_L03)}}, + {ID(I3), {1, ID(INIT_L03)}}, + {ID(I4), {0, ID(INIT_L20)}}, + }, ID(INIT_L20)}}, + }; + + + void find_inverted_bits() + { + for (auto cell : module->selected_cells()) { + if (cell->type != ID($__CC_NOT)) + continue; + SigBit a = sigmap(cell->getPort(ID::A)[0]); + SigBit y = sigmap(cell->getPort(ID::Y)[0]); + inverted_bits[y] = a; + inverter_input[a] = cell; + } + } + + Const invert_lut_input(Const lut, int bit) + { + Const result(State::S0, GetSize(lut)); + for (int i = 0; i < GetSize(lut); i++) { + int j = i ^ (1 << bit); + result[j] = lut[i]; + } + return result; + } + + Const invert_lut_output(Const lut) + { + Const result(State::S0, GetSize(lut)); + for (int i = 0; i < GetSize(lut); i++) + result[i] = (lut[i] == State::S1) ? State::S0 : State::S1; + return result; + } + + void fold_input_inverters() + { + for (auto cell : module->selected_cells()) { + auto found_type = lut_types.find(cell->type); + if (found_type == lut_types.end()) + continue; + const auto &type = found_type->second; + for (const auto &ipin : type.inputs) { + if (!cell->hasPort(ipin.first)) + continue; + auto sig = cell->getPort(ipin.first); + if (GetSize(sig) == 0) + continue; + SigBit bit = sigmap(sig[0]); + auto inv = inverted_bits.find(bit); + if (inv == inverted_bits.end()) + continue; // not the output of an inverter + // Rewire to inverter input + cell->unsetPort(ipin.first); + cell->setPort(ipin.first, inv->second); + // Rewrite init + cell->setParam(ipin.second.init_param, + invert_lut_input(cell->getParam(ipin.second.init_param), ipin.second.input_bit)); + } + } + } + + void fold_output_inverters() + { + pool<SigBit> used_bits; + // Find bits that are actually used + for (auto cell : module->selected_cells()) { + for (auto conn : cell->connections()) { + if (cell->output(conn.first)) + continue; + for (auto bit : sigmap(conn.second)) + used_bits.insert(bit); + } + } + // Find LUTs driving inverters + // (create a vector to avoid iterate-and-modify issues) + std::vector<std::pair<Cell *, Cell*>> lut_inv; + for (auto cell : module->selected_cells()) { + auto found_type = lut_types.find(cell->type); + if (found_type == lut_types.end()) + continue; + if (!cell->hasPort(ID::O)) + continue; + auto o_sig = cell->getPort(ID::O); + if (GetSize(o_sig) == 0) + continue; + SigBit o = sigmap(o_sig[0]); + auto found_inv = inverter_input.find(o); + if (found_inv == inverter_input.end()) + continue; // doesn't drive an inverter + lut_inv.emplace_back(cell, found_inv->second); + } + for (auto pair : lut_inv) { + Cell *orig_lut = pair.first; + Cell *inv = pair.second; + // Find the inverter output + SigBit inv_y = sigmap(inv->getPort(ID::Y)[0]); + // Inverter output might not actually be used; if all users were folded into inputs already + if (!used_bits.count(inv_y)) + continue; + // Create a duplicate of the LUT with an inverted output + // (if the uninverted version becomes unused it will be swept away) + Cell *dup_lut = module->addCell(NEW_ID, orig_lut->type); + inv->unsetPort(ID::Y); + dup_lut->setPort(ID::O, inv_y); + for (auto conn : orig_lut->connections()) { + if (conn.first == ID::O) + continue; + dup_lut->setPort(conn.first, conn.second); + } + for (auto param : orig_lut->parameters) { + if (param.first == lut_types.at(orig_lut->type).output_param) + dup_lut->parameters[param.first] = invert_lut_output(param.second); + else + dup_lut->parameters[param.first] = param.second; + } + } + } + + void operator()() + { + find_inverted_bits(); + fold_input_inverters(); + fold_output_inverters(); + } +}; + +struct GatemateFoldInvPass : public Pass { + GatemateFoldInvPass() : Pass("gatemate_foldinv", "fold inverters into Gatemate LUT trees") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" gatemate_foldinv [selection]\n"); + log("\n"); + log("\n"); + log("This pass searches for $__CC_NOT cells and folds them into CC_LUT2, CC_L2T4\n"); + log("and CC_L2T5 cells as created by LUT tree mapping.\n"); + log("\n"); + } + + void execute(std::vector<std::string> args, RTLIL::Design *design) override + { + log_header(design, "Executing GATEMATE_FOLDINV pass (folding LUT tree inverters).\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (Module *module : design->selected_modules()) { + FoldInvWorker worker(module); + worker(); + } + } +} GatemateFoldInvPass; + +PRIVATE_NAMESPACE_END + diff --git a/techlibs/gatemate/inv_map.v b/techlibs/gatemate/inv_map.v new file mode 100644 index 000000000..8a5051747 --- /dev/null +++ b/techlibs/gatemate/inv_map.v @@ -0,0 +1,4 @@ +// Any inverters not folded into LUTs are mapped to a LUT of their own +module \$__CC_NOT (input A, output Y); + CC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y)); +endmodule diff --git a/techlibs/gatemate/make_lut_tree_lib.py b/techlibs/gatemate/make_lut_tree_lib.py new file mode 100644 index 000000000..25ca88882 --- /dev/null +++ b/techlibs/gatemate/make_lut_tree_lib.py @@ -0,0 +1,323 @@ +#!/usr/bin/env python3 + +class FNode: + def __init__(self, fun, *args): + self.fun = fun + self.args = args + + if len(self.args) == 0: + assert fun not in ("BUF", "NOT", "AND", "OR", "XOR", "MUX") + + if len(self.args) == 1: + assert fun in ("BUF", "NOT") + + if len(self.args) == 2: + assert fun in ("AND", "OR", "XOR") + + if len(self.args) == 3: + assert fun in ("MUX") + + def __str__(self): + if len(self.args) == 0: + return self.fun + if self.fun == "NOT" and len(self.args[0].args) == 0: + return "!" + self.args[0].fun + return self.fun + "(" + ",".join([str(a) for a in self.args]) + ")" + + def as_genlib_term(self): + if len(self.args) == 0: + return self.fun + if self.fun == "NOT": + assert len(self.args[0].args) == 0 + return "!" + self.args[0].fun + if self.fun == "AND": + return "(" + self.args[0].as_genlib_term() + "*" + self.args[1].as_genlib_term() + ")" + if self.fun == "OR": + return "(" + self.args[0].as_genlib_term() + "+" + self.args[1].as_genlib_term() + ")" + assert False + + def mapMux(self): + if self.fun == "MUX": + A, B, C = self.args + return OR(AND(A, NOT(C)), AND(B, C)).mapMux() + return FNode(self.fun, *[a.mapMux() for a in self.args]) + + def mapXor(self): + if self.fun == "XOR": + A, B = self.args + return OR(AND(A, NOT(B)), AND(NOT(A), B)).mapXor() + return FNode(self.fun, *[a.mapXor() for a in self.args]) + + def mapNot(self): + if self.fun == "BUF": + return self.arg1.mapNot() + if self.fun == "NOT": + if self.args[0].fun == "AND": + return OR(NOT(self.args[0].args[0]),NOT(self.args[0].args[1])).mapNot() + if self.args[0].fun == "OR": + return AND(NOT(self.args[0].args[0]),NOT(self.args[0].args[1])).mapNot() + if self.args[0].fun == "NOT": + return self.args[0].args[0].mapNot() + return FNode(self.fun, *[a.mapNot() for a in self.args]) + + def map(self): + n = self + n = n.mapMux() + n = n.mapXor() + n = n.mapNot() + return n + + def isInv(self): + if len(self.args) == 0: + return False + if self.fun == "XOR": + return False + if self.fun == "NOT": + return self.args[0].isNonInv() + for a in self.args: + if not a.isInv(): + return False + return True + + def isNonInv(self): + if len(self.args) == 0: + return True + if self.fun == "XOR": + return False + if self.fun == "NOT": + return self.args[0].isInv() + for a in self.args: + if not a.isNonInv(): + return False + return True + +A = FNode("A") +B = FNode("B") +C = FNode("C") +D = FNode("D") +E = FNode("E") + +def BUF(arg): return FNode("BUF", arg) +def NOT(arg): return FNode("NOT", arg) +def AND(arg1, arg2): return FNode("AND", arg1, arg2) +def OR(arg1, arg2): return FNode( "OR", arg1, arg2) +def XOR(arg1, arg2): return FNode("XOR", arg1, arg2) +def MUX(arg1, arg2, arg3): return FNode("MUX", arg1, arg2, arg3) + +# Genlib Format: +# +# GATE <cell-name> <cell-area> <cell-logic-function> +# +# PIN <pin-name> <phase> <input-load> <max-load> +# <rise-block-delay> <rise-fanout-delay> +# <fall-block-delay> <fall-fanout-delay> +# +# phase: +# INV, NONINV, or UNKNOWN +# +# cell-logic-function: +# <output> = <term with *(AND), +(OR), !(NOT)> + + +cells = [ + ["$__CC_BUF", 5, A], + ["$__CC_NOT", 0, NOT(A)], + ["$__CC_MUX", 5, MUX(A, B, C)], +] + +base_cells = [ + ["$__CC2_A", AND(A, B)], + ["$__CC2_O", OR(A, B)], + ["$__CC2_X", XOR(A, B)], + + ["$__CC3_AA", AND(AND(A, B), C)], + ["$__CC3_OO", OR( OR(A, B), C)], + ["$__CC3_XX", XOR(XOR(A, B), C)], + ["$__CC3_AO", OR(AND(A, B), C)], + ["$__CC3_OA", AND( OR(A, B), C)], + ["$__CC3_AX", XOR(AND(A, B), C)], + ["$__CC3_XA", AND(XOR(A, B), C)], + +# ["$__CC3_AAA", AND(AND(A,B),AND(A,C))], +# ["$__CC3_AXA", XOR(AND(A,B),AND(A,C))], +# ["$__CC3_XAX", AND(XOR(A,B),XOR(A,C))], +# ["$__CC3_AAX", AND(AND(A,B),XOR(A,C))], +# ["$__CC3_AXX", XOR(AND(A,B),XOR(A,C))], +# ["$__CC3_XXX", XOR(XOR(A,B),XOR(A,C))], +# ["$__CC3_AAO", AND(AND(A,B), OR(A,C))], +# ["$__CC3_AOA", OR(AND(A,B),AND(A,C))], +# ["$__CC3_AOX", OR(AND(A,B),XOR(A,C))], + +# ["$__CC3_AAA_N", AND(AND(A,B),AND(NOT(A),C))], +# ["$__CC3_AXA_N", XOR(AND(A,B),AND(NOT(A),C))], +# ["$__CC3_XAX_N", AND(XOR(A,B),XOR(NOT(A),C))], +# ["$__CC3_AAX_N", AND(AND(A,B),XOR(NOT(A),C))], +# ["$__CC3_AXX_N", XOR(AND(A,B),XOR(NOT(A),C))], +# ["$__CC3_XXX_N", XOR(XOR(A,B),XOR(NOT(A),C))], +# ["$__CC3_AAO_N", AND(AND(A,B), OR(NOT(A),C))], +# ["$__CC3_AOA_N", OR(AND(A,B),AND(NOT(A),C))], +# ["$__CC3_AOX_N", OR(AND(A,B),XOR(NOT(A),C))], + + ["$__CC4_AAA", AND(AND(A,B),AND(C,D))], + ["$__CC4_AXA", XOR(AND(A,B),AND(C,D))], + ["$__CC4_XAX", AND(XOR(A,B),XOR(C,D))], + ["$__CC4_AAX", AND(AND(A,B),XOR(C,D))], + ["$__CC4_AXX", XOR(AND(A,B),XOR(C,D))], + ["$__CC4_XXX", XOR(XOR(A,B),XOR(C,D))], + ["$__CC4_AAO", AND(AND(A,B), OR(C,D))], + ["$__CC4_AOA", OR(AND(A,B),AND(C,D))], + ["$__CC4_AOX", OR(AND(A,B),XOR(C,D))], +] + +for name, expr in base_cells: + cells.append([name, 10, expr]) + + name = (name + .replace("$__CC4_", "$__CC5_") + .replace("$__CC3_", "$__CC4_") + .replace("$__CC2_", "$__CC3_")) + + # Cells such as $__CC4_AA_A are redundant, as $__CC4_AAA is equivalent + if name not in ("$__CC4_AA", "$__CC3_A"): + cells.append([name + "_A", 12, AND(E, expr)]) + if name not in ("$__CC4_OO", "$__CC3_O"): + cells.append([name + "_O", 12, OR(E, expr)]) + if name not in ("$__CC4_XX", "$__CC3_X"): + cells.append([name + "_X", 12, XOR(E, expr)]) + +with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf: + def mkGate(name, cost, expr, max_load=9999, block_delay = 10, fanout_delay = 5): + name = name.replace(" ", "") + expr = expr.map() + + phase = "UNKNOWN" + if expr.isInv(): phase = "INV" + if expr.isNonInv(): phase = "NONINV" + + print("", file=glf) + print("GATE %s %d Y=%s;" % (name, cost, expr.as_genlib_term()), file=glf) + print("PIN * %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf) + print("GATE $__ZERO 0 Y=CONST0;", file=glf) + print("GATE $__ONE 0 Y=CONST1;", file=glf) + for name, cost, expr in cells: + mkGate(name, cost, expr) + +class LUTTreeNode: + def __init__(self, name, width, inputs=None): + self.name = name + self.width = width + self.inputs = inputs + def is_input(self): + return self.width == 0 + def map(self, expr, params, ports): + if self.is_input(): + # Input to LUT tree + if expr is None: + ports[self.name] = "" # disconnected input + else: + assert(len(expr.args) == 0) + ports[self.name] = expr.fun + return + if expr is None: + # Unused part of tree + params[self.name] = "4'b0000" + for i in self.inputs: + i.map(None, params, ports) + return + elif len(expr.args) == 0: + # Input to the expression; but not LUT tree + # Insert a route through + params[self.name] = "4'b1010" + self.inputs[0].map(expr, params, ports) + for i in self.inputs[1:]: + i.map(None, params, ports) + return + # Map uphill LUTs; uninverting arguments and keeping track of that if needed + arg_inv = [] + for (i, arg) in zip(self.inputs, expr.args): + if arg.fun == "NOT": + i.map(arg.args[0], params, ports) + arg_inv.append(True) + else: + i.map(arg, params, ports) + arg_inv.append(False) + # Determine base init value + assert self.width == 2 + if expr.fun == "AND": + init = 0b1000 + elif expr.fun == "OR": + init = 0b1110 + elif expr.fun == "XOR": + init = 0b0110 + else: + assert False, expr.fun + # Swap bits if init inverted + swapped_init = 0b0000 + for b in range(4): + if ((init >> b) & 0x1) == 0: continue + for i in range(2): + if arg_inv[i]: + b ^= (1 << i) + swapped_init |= (1 << b) + # Set init param + params[self.name] = "4'b{:04b}".format(swapped_init) + +def LUT2(name, i0, i1): return LUTTreeNode(name, 2, [i0, i1]) +def I(name): return LUTTreeNode(name, 0) + +lut_prims = { + "CC_LUT2": LUT2("INIT", I("I0"), I("I1")), + "CC_L2T4": LUT2( + "INIT_L10", + LUT2("INIT_L00", I("I0"), I("I1")), + LUT2("INIT_L01", I("I2"), I("I3")), + ), + "CC_L2T5": LUT2( + "INIT_L20", I("I4"), LUT2("INIT_L11", + LUT2("INIT_L02", I("I0"), I("I1")), + LUT2("INIT_L03", I("I2"), I("I3")), + ) + ) +} + +with open("techlibs/gatemate/lut_tree_map.v", "w") as vf: + # Non-automatic rules + print(""" +module \\$__ZERO (output Y); assign Y = 1'b0; endmodule +module \\$__ONE (output Y); assign Y = 1'b1; endmodule + +module \\$__CC_BUF (input A, output Y); assign Y = A; endmodule + +module \\$__CC_MUX (input A, B, C, output Y); + CC_MX2 _TECHMAP_REPLACE_ ( + .D0(A), .D1(B), .S0(C), + .Y(Y) + ); +endmodule +""", file=vf) + for name, cost, expr in cells: + expr = expr.mapMux().mapNot() # Don't map XOR + if name in ("$__CC_BUF", "$__CC_NOT", "$__CC_MUX"): + # Special cases + continue + if name.startswith("$__CC2_"): + prim = "CC_LUT2" + elif name.startswith("$__CC5_") or (name.startswith("$__CC4_") and cost == 12): + prim = "CC_L2T5" + else: + prim = "CC_L2T4" + ports = {} + params = {} + lut_prims[prim].map(expr, params, ports) + print("", file=vf) + print("module \\%s (input %s, output Y);" % (name, + ", ".join(sorted(set(x for x in ports.values() if x)))), file=vf) + print(" %s #(" % prim, file=vf) + for k, v in sorted(params.items(), key=lambda x: x[0]): + print(" .%s(%s)," % (k, v), file=vf) + print(" ) _TECHMAP_REPLACE_ (", file=vf) + print(" %s," % ", ".join(".%s(%s)" % (k, v) for k, v in sorted(ports.items(), key=lambda x:x[0])), + file=vf) + print(" .O(Y)", file=vf) + print(" );", file=vf) + print("endmodule", file=vf) diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index 93b16b2e0..dd4fde643 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -67,7 +67,10 @@ struct SynthGateMatePass : public ScriptPass log("\n");
log(" -nomx8, -nomx4\n");
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
- log("\n");;
+ log("\n");
+ log(" -luttree\n");
+ log(" use new LUT tree mapping approach (EXPERIMENTAL).\n");
+ log("\n");
log(" -dff\n");
log(" run 'abc' with -dff option\n");
log("\n");
@@ -87,7 +90,7 @@ struct SynthGateMatePass : public ScriptPass }
string top_opt, vlog_file, json_file;
- bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, dff, retime, noiopad, noclkbuf;
+ bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf;
void clear_flags() override
{
@@ -100,6 +103,7 @@ struct SynthGateMatePass : public ScriptPass nomult = false;
nomx4 = false;
nomx8 = false;
+ luttree = false;
dff = false;
retime = false;
noiopad = false;
@@ -158,6 +162,10 @@ struct SynthGateMatePass : public ScriptPass nomx8 = true;
continue;
}
+ if (args[argidx] == "-luttree") {
+ luttree = true;
+ continue;
+ }
if (args[argidx] == "-dff") {
dff = true;
continue;
@@ -298,11 +306,23 @@ struct SynthGateMatePass : public ScriptPass if (check_label("map_luts"))
{
- std::string abc_args = " -dress -lut 4";
- if (dff) {
- abc_args += " -dff";
+ if (luttree || help_mode) {
+ std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib";
+ if (dff) {
+ abc_args += " -dff";
+ }
+ run("abc " + abc_args, "(with -luttree)");
+ run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
+ run("gatemate_foldinv", "(with -luttree)");
+ run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
+ }
+ if (!luttree || help_mode) {
+ std::string abc_args = " -dress -lut 4";
+ if (dff) {
+ abc_args += " -dff";
+ }
+ run("abc " + abc_args, "(without -luttree)");
}
- run("abc " + abc_args);
run("clean");
}
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 736aa0707..ab8207ef1 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -1553,6 +1553,53 @@ parameter DEVICE = "GW1N-1"; // "GW1N-1", "GW1N-4", "GW1N-9", "GW1NR-4", endmodule (* blackbox *) +module PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN); +input CLKIN; +input CLKFB; +input RESET; +input RESET_P; +input [5:0] FBDSEL; +input [5:0] IDSEL; +input [5:0] ODSEL; +input [3:0] PSDA,FDLY; +input [3:0] DUTYDA; +input VREN; + +output CLKOUT; +output LOCK; +output CLKOUTP; +output CLKOUTD; +output CLKOUTD3; + +parameter FCLKIN = "100.0"; // frequency of CLKIN +parameter DYN_IDIV_SEL= "false"; // true:IDSEL, false:IDIV_SEL +parameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64 +parameter DYN_FBDIV_SEL= "false"; // true:FBDSEL, false:FBDIV_SEL +parameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64 +parameter DYN_ODIV_SEL= "false"; // true:ODSEL, false:ODIV_SEL +parameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128 + +parameter PSDA_SEL= "0000"; +parameter DYN_DA_EN = "false"; // true:PSDA or DUTYDA or FDA, false: DA_SEL +parameter DUTYDA_SEL= "1000"; + +parameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only +parameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only +parameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4 +parameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2 + +parameter CLKFB_SEL = "internal"; // "internal", "external" +parameter CLKOUT_BYPASS = "false"; // "true", "false" +parameter CLKOUTP_BYPASS = "false"; // "true", "false" +parameter CLKOUTD_BYPASS = "false"; // "true", "false" +parameter DYN_SDIV_SEL = 2; // 2~128, only even numbers +parameter CLKOUTD_SRC = "CLKOUT"; // CLKOUT, CLKOUTP +parameter CLKOUTD3_SRC = "CLKOUT"; // CLKOUT, CLKOUTP +parameter DEVICE = "GW1NS-4"; // "GW1NS-4", "GW1NS-4C", "GW1NSR-4", "GW1NSR-4C", "GW1NSER-4C" + +endmodule + +(* blackbox *) module OSC(OSCOUT); output OSCOUT; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 15a0c41e0..0dffdf498 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -131,7 +131,6 @@ struct SynthGowinPass : public ScriptPass if (args[argidx] == "-json" && argidx+1 < args.size()) { json_file = args[++argidx]; nobram = true; - nolutram = true; continue; } if (args[argidx] == "-run" && argidx+1 < args.size()) { diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2e1c6807a..52e8e2e3a 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -302,7 +302,9 @@ endmodule (* abc9_flop, lib_whitebox *) module SB_DFFE ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input D ); `SB_DFF_INIT @@ -589,7 +591,10 @@ endmodule (* abc9_flop, lib_whitebox *) module SB_DFFESR ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input R, + input D ); `SB_DFF_INIT @@ -647,7 +652,10 @@ endmodule (* abc9_box, lib_whitebox *) module SB_DFFER ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input R, + input D ); `SB_DFF_INIT @@ -724,7 +732,10 @@ endmodule (* abc9_flop, lib_whitebox *) module SB_DFFESS ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input S, + input D ); `SB_DFF_INIT @@ -782,7 +793,10 @@ endmodule (* abc9_box, lib_whitebox *) module SB_DFFES ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input S, + input D ); `SB_DFF_INIT @@ -899,7 +913,9 @@ endmodule (* abc9_flop, lib_whitebox *) module SB_DFFNE ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input D ); `SB_DFF_INIT @@ -1186,7 +1202,10 @@ endmodule (* abc9_flop, lib_whitebox *) module SB_DFFNESR ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input R, + input D ); `SB_DFF_INIT @@ -1244,7 +1263,10 @@ endmodule (* abc9_box, lib_whitebox *) module SB_DFFNER ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input R, + input D ); `SB_DFF_INIT @@ -1321,7 +1343,10 @@ endmodule (* abc9_flop, lib_whitebox *) module SB_DFFNESS ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input S, + input D ); `SB_DFF_INIT @@ -1379,7 +1404,10 @@ endmodule (* abc9_box, lib_whitebox *) module SB_DFFNES ( output reg Q, - input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D + input C, + input E `ICE40_DEFAULT_ASSIGNMENT_1, + input S, + input D ); `SB_DFF_INIT diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 1174f6e04..2ae859efe 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -45,8 +45,8 @@ struct SynthIce40Pass : public ScriptPass log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -device < hx | lp | u >\n"); - log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n"); - log(" default: hx\n"); + log(" relevant only for '-abc9' flow, optimise timing for the specified\n"); + log(" device. default: hx\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module\n"); diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 166c81843..e9594e6d8 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -39,21 +39,22 @@ struct SynthIntelPass : public ScriptPass { log(" -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); - log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); - log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n"); + log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use\n"); + log(" cycloneive. For Cyclone V and Cyclone 10 GX, use the synth_intel_alm\n"); + log(" backend instead.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); log("\n"); log(" -vqm <file>\n"); - log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" write the design to the specified Verilog Quartus Mapping File. Writing\n"); + log(" of an output file is omitted if this parameter is not specified.\n"); log(" Note that this backend has not been tested and is likely incompatible\n"); log(" with recent versions of Quartus.\n"); log("\n"); log(" -vpr <file>\n"); - log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); - log(" compatible with the Quartus flow. Writing of an\n"); + log(" write BLIF files for VPR flow experiments. The synthesized BLIF output\n"); + log(" file is not compatible with the Quartus flow. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 43d3592d5..c33eb43bf 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -43,21 +43,24 @@ struct SynthIntelALMPass : public ScriptPass { log(" -family <family>\n"); log(" target one of:\n"); log(" \"cyclonev\" - Cyclone V (default)\n"); - log(" \"arriav\" - Arria V (non-GZ)"); + log(" \"arriav\" - Arria V (non-GZ)\n"); log(" \"cyclone10gx\" - Cyclone 10GX\n"); log("\n"); log(" -vqm <file>\n"); - log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); - log(" output file is omitted if this parameter is not specified. Implies -quartus.\n"); + log(" write the design to the specified Verilog Quartus Mapping File. Writing\n"); + log(" of an output file is omitted if this parameter is not specified. Implies\n"); + log(" -quartus.\n"); log("\n"); log(" -noflatten\n"); - log(" do not flatten design before synthesis; useful for per-module area statistics\n"); + log(" do not flatten design before synthesis; useful for per-module area\n"); + log(" statistics\n"); log("\n"); log(" -quartus\n"); log(" output a netlist using Quartus cells instead of MISTRAL_* cells\n"); log("\n"); log(" -dff\n"); - log(" pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n"); + log(" pass DFFs to ABC to perform sequential logic optimisations\n"); + log(" (EXPERIMENTAL)\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); diff --git a/techlibs/nexus/brams_map.v b/techlibs/nexus/brams_map.v index 3cada2414..cec56cec4 100644 --- a/techlibs/nexus/brams_map.v +++ b/techlibs/nexus/brams_map.v @@ -32,10 +32,10 @@ output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; function [319:0] init_slice; input integer idx; - integer i, j; + integer i; init_slice = 0; - for (i = 0; i < 16; i = i + 1) begin - init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + for (i = 0; i < 32; i = i + 1) begin + init_slice[i*10+:9] = INIT[(idx * 32 + i) * 9+:9]; end endfunction @@ -43,8 +43,28 @@ wire [17:0] DOA; wire [17:0] DOB; wire [17:0] DIA = PORT_A_WR_DATA; wire [17:0] DIB = PORT_B_WR_DATA; -wire [13:0] ADA = PORT_A_WIDTH == 18 ? {PORT_A_ADDR[13:2], PORT_A_WR_BE} : PORT_A_ADDR; -wire [13:0] ADB = PORT_B_WIDTH == 18 ? {PORT_B_ADDR[13:2], PORT_B_WR_BE} : PORT_B_ADDR; +wire [13:0] ADA; +wire [13:0] ADB; + +generate + +case(PORT_A_WIDTH) +1: assign ADA = PORT_A_ADDR; +2: assign ADA = {PORT_A_ADDR[13:1], 1'b1}; +4: assign ADA = {PORT_A_ADDR[13:2], 2'b11}; +9: assign ADA = {PORT_A_ADDR[13:3], 3'b111}; +18: assign ADA = {PORT_A_ADDR[13:4], 2'b11, PORT_A_WR_BE}; +endcase + +case(PORT_B_WIDTH) +1: assign ADB = PORT_B_ADDR; +2: assign ADB = {PORT_B_ADDR[13:1], 1'b1}; +4: assign ADB = {PORT_B_ADDR[13:2], 2'b11}; +9: assign ADB = {PORT_B_ADDR[13:3], 3'b111}; +18: assign ADB = {PORT_B_ADDR[13:4], 2'b11, PORT_B_WR_BE}; +endcase + +endgenerate assign PORT_A_RD_DATA = DOA; assign PORT_B_RD_DATA = DOB; @@ -122,8 +142,8 @@ DP16K #( .RESETMODE_B(PORT_B_OPTION_RESETMODE), .ASYNC_RST_RELEASE_A(PORT_A_OPTION_RESETMODE), .ASYNC_RST_RELEASE_B(PORT_B_OPTION_RESETMODE), - .CSDECODE_A("000"), - .CSDECODE_B("000"), + .CSDECODE_A("111"), + .CSDECODE_B("111"), .GSR("DISABLED"), ) _TECHMAP_REPLACE_ ( .CLKA(PORT_A_CLK), @@ -176,10 +196,10 @@ input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; function [319:0] init_slice; input integer idx; - integer i, j; + integer i; init_slice = 0; - for (i = 0; i < 16; i = i + 1) begin - init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + for (i = 0; i < 32; i = i + 1) begin + init_slice[i*10+:9] = INIT[(idx * 32 + i) * 9+:9]; end endfunction @@ -188,11 +208,29 @@ wire [35:0] DO; assign PORT_R_RD_DATA = DO; -wire [13:0] ADW = PORT_W_WIDTH == 36 ? {PORT_W_ADDR[13:4], PORT_W_WR_EN} : - (PORT_W_WIDTH == 18 ? {PORT_W_ADDR[13:2], PORT_W_WR_EN} : PORT_W_ADDR); +wire [13:0] ADW; +wire [13:0] ADR; generate +case (PORT_W_WIDTH) +1: assign ADW = PORT_W_ADDR; +2: assign ADW = {PORT_W_ADDR[13:1], 1'b1}; +4: assign ADW = {PORT_W_ADDR[13:2], 2'b11}; +9: assign ADW = {PORT_W_ADDR[13:3], 3'b111}; +18: assign ADW = {PORT_W_ADDR[13:4], 2'b11, PORT_W_WR_EN}; +36: assign ADW = {PORT_W_ADDR[13:5], 1'b1, PORT_W_WR_EN}; +endcase + +case (PORT_R_WIDTH) +1: assign ADR = PORT_R_ADDR; +2: assign ADR = {PORT_R_ADDR[13:1], 1'b1}; +4: assign ADR = {PORT_R_ADDR[13:2], 2'b11}; +9: assign ADR = {PORT_R_ADDR[13:3], 3'b111}; +18: assign ADR = {PORT_R_ADDR[13:4], 4'b1111}; +36: assign ADR = {PORT_R_ADDR[13:5], 5'b11111}; +endcase + if (OPTION_SAME_CLOCK) begin PDPSC16K #( @@ -265,14 +303,14 @@ PDPSC16K #( .OUTREG("BYPASSED"), .RESETMODE(PORT_R_OPTION_RESETMODE), .ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE), - .CSDECODE_W("000"), - .CSDECODE_R("000"), + .CSDECODE_W("111"), + .CSDECODE_R("111"), .ECC("DISABLED"), .GSR("DISABLED"), ) _TECHMAP_REPLACE_ ( .CLK(CLK_C), - .CEW(PORT_W_CLK_EN), + .CEW(PORT_W_CLK_EN & (|PORT_W_WR_EN)), .CSW(3'b111), .ADW(ADW), .DI(DI), @@ -280,7 +318,7 @@ PDPSC16K #( .CER(PORT_R_CLK_EN), .RST(PORT_R_OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST), .CSR(3'b111), - .ADR(PORT_R_ADDR), + .ADR(ADR), .DO(DO), ); @@ -356,13 +394,13 @@ PDP16K #( .OUTREG("BYPASSED"), .RESETMODE(PORT_R_OPTION_RESETMODE), .ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE), - .CSDECODE_W("000"), - .CSDECODE_R("000"), + .CSDECODE_W("111"), + .CSDECODE_R("111"), .ECC("DISABLED"), .GSR("DISABLED"), ) _TECHMAP_REPLACE_ ( .CLKW(PORT_W_CLK), - .CEW(PORT_W_CLK_EN), + .CEW(PORT_W_CLK_EN & (|PORT_W_WR_EN)), .CSW(3'b111), .ADW(ADW), .DI(DI), @@ -371,7 +409,7 @@ PDP16K #( .CER(PORT_R_CLK_EN), .RST(PORT_R_OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST), .CSR(3'b111), - .ADR(PORT_R_ADDR), + .ADR(ADR), .DO(DO), ); diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 754de2de6..94bd44db0 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -48,8 +48,8 @@ struct SynthQuickLogicPass : public ScriptPass { log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -verilog <file>\n"); - log(" write the design to the specified verilog file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); + log(" write the design to the specified verilog file. writing of an output\n"); + log(" file is omitted if this parameter is not specified.\n"); log("\n"); log(" -abc\n"); log(" use old ABC flow, which has generally worse mapping results but is less\n"); diff --git a/techlibs/sf2/NOTES.txt b/techlibs/sf2/NOTES.txt new file mode 100644 index 000000000..67784b546 --- /dev/null +++ b/techlibs/sf2/NOTES.txt @@ -0,0 +1,84 @@ +Using yosys with Libero Soc +=========================== + +Yosys does synthesis and therefore could be used instead of Synplify in +the Libero workflow. You still have to use LiberoSoc for place, route, +bitsteam generation, timing analysis... + +This is unfortunately not trivial, but this is also not too difficult. +When you run the Synthesize step, three tools are executed one after the other. + +You'd better to write a simple script, like this one (assuming the top module +is top): + +----------- run_yosys.sh -------------- +#!/bin/sh + +set -e + +yosys -p 'read_verilog hdl/top.v; synth_sf2; write_verilog -defparam synthesis/top_yosys.v' + +rwnetlist64 --script yosys/rwnetlist.tcl + +echo "##### run g4compile" + +g4compile --script yosys/run_compile.tcl + +libero SCRIPT:run_yosys.tcl +------------------------------------ + +Yosys will do the synthesis and write a netlist in verilog. Then you have +to call microsemi tools to build the netlist for the P&R tools. + +The first one do a file format conversion. During the normal workflow, the +tcl file is created in a temporary file. You can use this one: + +------------- tcl/rwnetlist.tcl --------- +set_device -fam SmartFusion2 +read_verilog \ + -file {../synthesis/top_yosys.v} +write_adl -file {../designer/top/top.adl} +---------------------------------------- + +Probably, you will have to change the family for Igloo2. + +The second command link the netlists. The tcl script is generated by +liberoSoc in designer/top/run_compile.tcl. You can use it as it. +The "Source Files" value could be changed but it looks to have no effect. +This commands create the .afl file. + +Then you can use the normal flow. This is done by the run_yosys.tcl: + +----------- run_yosys.tcl -------------- +open_project -file {./top.prjx} +run_tool -name {PLACEROUTE} +run_tool -name {PROGRAMDEVICE} +----------------------------------------- + + +Using MSS, HPMS or other IPs +============================ + +This works. You'd better to configure CCC (~ the PLL) and the MSS using +liberoSoc as the configuration bits are not documented. +Then you have to manually gather the HDL sources generated for the IPs. +They are in the component subdirectory. Sometimes there are both a _syn and +a _pre version of the same file. They are for symplify and precision. +Use only once, the symplify version should be OK. For the MSS, these are the +blackboxes, so you don't need them. + +SYSRESET and XTLOSC have one fake port. This is handled, provided you use +the blackbox module declared by Yosys in cell_sim.v. This is OK by default +too. + + +What is missing +=============== + +Always flatten your design (this is the default). Hierarchical designs +don't work. + +Constraints (SDC files) are not supported by Yosys. Furthermore, due to +flattening and optimization, nets name may change. + +More testing... diff --git a/techlibs/sf2/arith_map.v b/techlibs/sf2/arith_map.v index f16b1abb8..eb367799b 100644 --- a/techlibs/sf2/arith_map.v +++ b/techlibs/sf2/arith_map.v @@ -17,5 +17,53 @@ * */ +(* techmap_celltype = "$alu" *) +module \$__SF2_ALU (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] AA, BB; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB)); + + (* force_downto *) + wire [Y_WIDTH-1:0] C = {CO, CI}; + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice + ARI1 #( + // G = F1 = A[i] & (B[i]^BI) + // Y = F0 = A[i]^B[i]^BI + // P = Y + // ADCB + .INIT(20'b 01_11_0010_1000_1001_0110) + ) carry ( + .A(1'b0), + .B(AA[i]), + .C(BB[i]), + .D(BI), + .FCI(C[i]), + .Y(X[i]), + .S(Y[i]), + .FCO(CO[i]) + ); + end endgenerate +endmodule -// nothing here yet diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index 4b57bad7b..b5438e44c 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -152,12 +152,26 @@ module SLE ( assign Q = LAT ? q_latch : q_ff; endmodule -// module AR1 +module ARI1 ( + input A, B, C, D, FCI, + output Y, S, FCO +); + parameter [19:0] INIT = 20'h0; + wire [2:0] Fsel = {D, C, B}; + wire F0 = INIT[Fsel]; + wire F1 = INIT[8 + Fsel]; + wire Yout = A ? F1 : F0; + assign Y = Yout; + assign S = FCI ^ Yout; + wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17]; + wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0); + assign FCO = P ? FCI : G; +endmodule + // module FCEND_BUFF // module FCINIT_BUFF // module FLASH_FREEZE // module OSCILLATOR -// module SYSRESET // module SYSCTRL_RESET_STATUS // module LIVE_PROBE_FB @@ -333,6 +347,7 @@ module BIBUF ( inout PAD, output Y ); + parameter IOSTD = ""; assign PAD = E ? D : 1'bz; assign Y = PAD; endmodule @@ -347,6 +362,7 @@ module BIBUF_DIFF ( inout PADN, output Y ); + parameter IOSTD = ""; endmodule module CLKBIBUF ( @@ -357,6 +373,7 @@ module CLKBIBUF ( (* clkbuf_driver *) output Y ); + parameter IOSTD = ""; assign PAD = E ? D : 1'bz; assign Y = PAD; endmodule @@ -367,6 +384,7 @@ module CLKBUF ( (* clkbuf_driver *) output Y ); + parameter IOSTD = ""; assign Y = PAD; endmodule @@ -379,6 +397,7 @@ module CLKBUF_DIFF ( (* clkbuf_driver *) output Y ); + parameter IOSTD = ""; endmodule module INBUF ( @@ -386,6 +405,7 @@ module INBUF ( input PAD, output Y ); + parameter IOSTD = ""; assign Y = PAD; endmodule @@ -397,6 +417,7 @@ module INBUF_DIFF ( input PADN, output Y ); + parameter IOSTD = ""; endmodule module OUTBUF ( @@ -404,6 +425,7 @@ module OUTBUF ( (* iopad_external_pin *) output PAD ); + parameter IOSTD = ""; assign PAD = D; endmodule @@ -415,6 +437,7 @@ module OUTBUF_DIFF ( (* iopad_external_pin *) output PADN ); + parameter IOSTD = ""; endmodule module TRIBUFF ( @@ -423,6 +446,7 @@ module TRIBUFF ( (* iopad_external_pin *) output PAD ); + parameter IOSTD = ""; assign PAD = E ? D : 1'bz; endmodule @@ -435,6 +459,7 @@ module TRIBUFF_DIFF ( (* iopad_external_pin *) output PADN ); + parameter IOSTD = ""; endmodule // module DDR_IN @@ -442,3 +467,113 @@ endmodule // module RAM1K18 // module RAM64x18 // module MACC + +(* blackbox *) +module SYSRESET ( + (* iopad_external_pin *) + input DEVRST_N, + output POWER_ON_RESET_N); +endmodule + + +(* blackbox *) +module XTLOSC ( + (* iopad_external_pin *) + input XTL, + output CLKOUT); + parameter [1:0] MODE = 2'h3; + parameter real FREQUENCY = 20.0; +endmodule + +(* blackbox *) +module RAM1K18 ( + input [13:0] A_ADDR, + input [2:0] A_BLK, + (* clkbuf_sink *) + input A_CLK, + input [17:0] A_DIN, + output [17:0] A_DOUT, + input [1:0] A_WEN, + input [2:0] A_WIDTH, + input A_WMODE, + input A_ARST_N, + input A_DOUT_LAT, + input A_DOUT_ARST_N, + (* clkbuf_sink *) + input A_DOUT_CLK, + input A_DOUT_EN, + input A_DOUT_SRST_N, + + input [13:0] B_ADDR, + input [2:0] B_BLK, + (* clkbuf_sink *) + input B_CLK, + input [17:0] B_DIN, + output [17:0] B_DOUT, + input [1:0] B_WEN, + input [2:0] B_WIDTH, + input B_WMODE, + input B_ARST_N, + input B_DOUT_LAT, + input B_DOUT_ARST_N, + (* clkbuf_sink *) + input B_DOUT_CLK, + input B_DOUT_EN, + input B_DOUT_SRST_N, + + input A_EN, + input B_EN, + input SII_LOCK, + output BUSY); +endmodule + +(* blackbox *) +module RAM64x18 ( + input [9:0] A_ADDR, + input [1:0] A_BLK, + input [2:0] A_WIDTH, + output [17:0] A_DOUT, + input A_DOUT_ARST_N, + (* clkbuf_sink *) + input A_DOUT_CLK, + input A_DOUT_EN, + input A_DOUT_LAT, + input A_DOUT_SRST_N, + (* clkbuf_sink *) + input A_ADDR_CLK, + input A_ADDR_EN, + input A_ADDR_LAT, + input A_ADDR_SRST_N, + input A_ADDR_ARST_N, + + input [9:0] B_ADDR, + input [1:0] B_BLK, + input [2:0] B_WIDTH, + output [17:0] B_DOUT, + input B_DOUT_ARST_N, + (* clkbuf_sink *) + input B_DOUT_CLK, + input B_DOUT_EN, + input B_DOUT_LAT, + input B_DOUT_SRST_N, + (* clkbuf_sink *) + input B_ADDR_CLK, + input B_ADDR_EN, + input B_ADDR_LAT, + input B_ADDR_SRST_N, + input B_ADDR_ARST_N, + + input [9:0] C_ADDR, + (* clkbuf_sink *) + input C_CLK, + input [17:0] C_DIN, + input C_WEN, + input [1:0] C_BLK, + input [2:0] C_WIDTH, + + input A_EN, + input B_EN, + input C_EN, + input SII_LOCK, + output BUSY); +endmodule diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 8d78a6097..bf4a6e031 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -45,8 +45,8 @@ struct SynthSf2Pass : public ScriptPass log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -vlog <file>\n"); - log(" write the design to the specified Verilog file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); + log(" write the design to the specified Verilog file. writing of an output\n"); + log(" file is omitted if this parameter is not specified.\n"); log("\n"); log(" -json <file>\n"); log(" write the design to the specified JSON file. writing of an output file\n"); @@ -66,6 +66,9 @@ struct SynthSf2Pass : public ScriptPass log(" -clkbuf\n"); log(" insert direct PAD->global_net buffers\n"); log("\n"); + log(" -discard-ffinit\n"); + log(" discard FF init value instead of emitting an error\n"); + log("\n"); log(" -retime\n"); log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); @@ -76,7 +79,7 @@ struct SynthSf2Pass : public ScriptPass } string top_opt, edif_file, vlog_file, json_file; - bool flatten, retime, iobs, clkbuf; + bool flatten, retime, iobs, clkbuf, discard_ffinit; void clear_flags() override { @@ -88,6 +91,7 @@ struct SynthSf2Pass : public ScriptPass retime = false; iobs = true; clkbuf = false; + discard_ffinit = false; } void execute(std::vector<std::string> args, RTLIL::Design *design) override @@ -138,6 +142,10 @@ struct SynthSf2Pass : public ScriptPass clkbuf = true; continue; } + if (args[argidx] == "-discard-ffinit") { + discard_ffinit = true; + continue; + } break; } extra_args(args, argidx, design); @@ -171,6 +179,8 @@ struct SynthSf2Pass : public ScriptPass if (check_label("coarse")) { + if (discard_ffinit || help_mode) + run("attrmap -remove init", "(only if -discard-ffinit)"); run("synth -run coarse"); } @@ -218,9 +228,9 @@ struct SynthSf2Pass : public ScriptPass } else { run("clkbufmap -buf CLKINT Y:A"); } - run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs"); + run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs)"); } - run("clean"); + run("clean -purge"); } if (check_label("check")) diff --git a/techlibs/sf2/tests/test_arith.ys b/techlibs/sf2/tests/test_arith.ys new file mode 100644 index 000000000..da7b96602 --- /dev/null +++ b/techlibs/sf2/tests/test_arith.ys @@ -0,0 +1,22 @@ +# Our implementation +read_verilog ../arith_map.v +read_verilog ../cells_sim.v +read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v +rename \$__SF2_ALU gate +hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5 +flatten +opt +write_verilog gate.v + +# The reference +read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v +rename \$alu gold +hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5 +flatten +proc +clean +write_verilog gold.v + +read_verilog gate.v +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6214e1411..a242cdef1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -93,7 +93,8 @@ struct SynthXilinxPass : public ScriptPass log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); log("\n"); log(" -nowidelut\n"); - log(" do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n"); + log(" do not use MUXF[5-9] resources to implement LUTs larger than native for\n"); + log(" the target\n"); log("\n"); log(" -nodsp\n"); log(" do not use DSP48*s to implement multipliers and associated logic\n"); @@ -109,8 +110,8 @@ struct SynthXilinxPass : public ScriptPass log(" infer URAM288s for large memories (xcup only)\n"); log("\n"); log(" -widemux <int>\n"); - log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n"); - log(" above this number of inputs (minimum value 2, recommended value >= 5).\n"); + log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n"); + log(" or above this number of inputs (minimum value 2, recommended value >= 5)\n"); log(" default: 0 (no inference)\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); |