diff options
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simcells.v | 4 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index d492c2f15..7c8a47ddd 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -20,12 +20,12 @@ * The internal logic cell simulation library. * * This verilog library contains simple simulation models for the internal - * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology + * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * */ -module \$_INV_ (A, Y); +module \$_NOT_ (A, Y); input A; output Y; assign Y = ~A; diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 7a4f6b272..190002c01 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -20,7 +20,7 @@ * The internal logic cell technology mapper. * * This verilog library contains the mapping of internal cells (e.g. $not with - * variable bit width) to the internal logic cells (such as the single bit $_INV_ + * variable bit width) to the internal logic cells (such as the single bit $_NOT_ * gate). Usually this logic network is then mapped to the actual technology * using e.g. the "abc" pass. * |