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-rw-r--r--techlibs/achronix/synth_achronix.cc2
-rw-r--r--techlibs/anlogic/cells_map.v38
-rw-r--r--techlibs/anlogic/cells_sim.v45
-rw-r--r--techlibs/anlogic/synth_anlogic.cc2
-rw-r--r--techlibs/efinix/Makefile.inc2
-rw-r--r--techlibs/efinix/cells_sim.v6
-rw-r--r--techlibs/efinix/efinix_gbuf.cc119
-rw-r--r--techlibs/efinix/gbuf_map.v3
-rw-r--r--techlibs/efinix/synth_efinix.cc3
9 files changed, 47 insertions, 173 deletions
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index ddd9822b9..b203828d2 100644
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -144,12 +144,12 @@ struct SynthAchronixPass : public ScriptPass {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
- run("dff2dffe -direct-match $_DFF_*");
run("opt -fine");
run("techmap -map +/techmap.v");
run("opt -full");
run("clean -purge");
run("setundef -undriven -zero");
+ run("dfflegalize -cell $_DFF_P_ x");
if (retime || help_mode)
run("abc -markgroups -dff -D 1", "(only if -retime)");
}
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index 0bcea9856..000256fb9 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -1,31 +1,17 @@
-module \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
-module \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(1'b0)); endmodule
+module \$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
-module \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
-module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
+module \$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
-
-module \$_DLATCH_N_ (E, D, Q);
- wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
- input E, D;
- output Q = !E ? D : Q;
-endmodule
-
-module \$_DLATCH_P_ (E, D, Q);
- wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
- input E, D;
- output Q = E ? D : Q;
-endmodule
+module \$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
`ifndef NO_LUT
module \$lut (A, Y);
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v
index 0fba43572..e8ecf4f03 100644
--- a/techlibs/anlogic/cells_sim.v
+++ b/techlibs/anlogic/cells_sim.v
@@ -10,9 +10,6 @@ module AL_MAP_SEQ (
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
- wire clk_ce;
- assign clk_ce = ce ? clk : 1'b0;
-
wire srmux;
generate
case (SRMUX)
@@ -20,7 +17,7 @@ module AL_MAP_SEQ (
"INV": assign srmux = ~sr;
default: assign srmux = sr;
endcase
- endgenerate
+ endgenerate
wire regset;
generate
@@ -34,43 +31,45 @@ module AL_MAP_SEQ (
initial q = regset;
generate
- if (DFFMODE == "FF")
+ if (DFFMODE == "FF")
begin
- if (SRMODE == "ASYNC")
+ if (SRMODE == "ASYNC")
begin
- always @(posedge clk_ce, posedge srmux)
+ always @(posedge clk, posedge srmux)
if (srmux)
q <= regset;
- else
- q <= d;
- end
+ else if (ce)
+ q <= d;
+ end
else
begin
- always @(posedge clk_ce)
+ always @(posedge clk)
if (srmux)
q <= regset;
- else
- q <= d;
+ else if (ce)
+ q <= d;
end
end
else
begin
// DFFMODE == "LATCH"
- if (SRMODE == "ASYNC")
+ if (SRMODE == "ASYNC")
begin
- always @(clk_ce, srmux)
+ always @*
if (srmux)
q <= regset;
- else
- q <= d;
- end
+ else if (~clk & ce)
+ q <= d;
+ end
else
begin
- always @(clk_ce)
- if (srmux)
- q <= regset;
- else
- q <= d;
+ always @*
+ if (~clk) begin
+ if (srmux)
+ q <= regset;
+ else if (ce)
+ q <= d;
+ end
end
end
endgenerate
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index d7475df86..d953fae5e 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -182,8 +182,8 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("map_ffs"))
{
+ run("dfflegalize -cell $_DFFE_P??P_ r -cell $_SDFFE_P??P_ r -cell $_DLATCH_N??_ r");
run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
- run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
run("opt_expr -mux_undef");
run("simplemap");
}
diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index 69665982c..2a3a953e3 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -1,10 +1,10 @@
OBJS += techlibs/efinix/synth_efinix.o
-OBJS += techlibs/efinix/efinix_gbuf.o
OBJS += techlibs/efinix/efinix_fixcarry.o
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/gbuf_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index a74d1c571..22c7bc776 100644
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -36,6 +36,7 @@ module EFX_FF(
output reg Q,
input D,
input CE,
+ (* clkbuf_sink *)
input CLK,
input SR
);
@@ -100,6 +101,7 @@ endmodule
module EFX_GBUFCE(
input CE,
input I,
+ (* clkbuf_driver *)
output O
);
parameter CE_POLARITY = 1'b1;
@@ -115,11 +117,13 @@ module EFX_RAM_5K(
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
+ (* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
+ (* clkbuf_sink *)
input RCLK
);
parameter READ_WIDTH = 20;
@@ -172,4 +176,4 @@ module EFX_RAM_5K(
(WRITE_WIDTH == 10) ? 9 : // 512x10
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
-endmodule \ No newline at end of file
+endmodule
diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc
deleted file mode 100644
index ae191359a..000000000
--- a/techlibs/efinix/efinix_gbuf.cc
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-static void handle_gbufs(Module *module)
-{
- SigMap sigmap(module);
-
- pool<SigBit> clk_bits;
- dict<SigBit, SigBit> rewrite_bits;
- vector<pair<Cell*, SigBit>> pad_bits;
-
- for (auto cell : module->cells())
- {
- if (cell->type == ID(EFX_FF)) {
- for (auto bit : sigmap(cell->getPort(ID::CLK)))
- clk_bits.insert(bit);
- }
- if (cell->type == ID(EFX_RAM_5K)) {
- for (auto bit : sigmap(cell->getPort(ID(RCLK))))
- clk_bits.insert(bit);
- for (auto bit : sigmap(cell->getPort(ID(WCLK))))
- clk_bits.insert(bit);
- }
- }
-
- for (auto wire : vector<Wire*>(module->wires()))
- {
- if (!wire->port_input)
- continue;
-
- for (int index = 0; index < GetSize(wire); index++)
- {
- SigBit bit(wire, index);
- SigBit canonical_bit = sigmap(bit);
-
- if (!clk_bits.count(canonical_bit))
- continue;
-
- Cell *c = module->addCell(NEW_ID, ID(EFX_GBUFCE));
- SigBit new_bit = module->addWire(NEW_ID);
- c->setParam(ID(CE_POLARITY), State::S1);
- c->setPort(ID::O, new_bit);
- c->setPort(ID(CE), State::S1);
- pad_bits.push_back(make_pair(c, bit));
- rewrite_bits[canonical_bit] = new_bit;
-
- log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
- }
- }
-
- auto rewrite_function = [&](SigSpec &s) {
- for (auto &bit : s) {
- SigBit canonical_bit = sigmap(bit);
- if (rewrite_bits.count(canonical_bit))
- bit = rewrite_bits.at(canonical_bit);
- }
- };
-
- module->rewrite_sigspecs(rewrite_function);
-
- for (auto &it : pad_bits)
- it.first->setPort(ID::I, it.second);
-}
-
-struct EfinixGbufPass : public Pass {
- EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
- void help() override
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" efinix_gbuf [options] [selection]\n");
- log("\n");
- log("Add Efinix global clock buffers to top module as needed.\n");
- log("\n");
- }
- void execute(std::vector<std::string> args, RTLIL::Design *design) override
- {
- log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- break;
- }
- extra_args(args, argidx, design);
-
- Module *module = design->top_module();
-
- if (module == nullptr)
- log_cmd_error("No top module found.\n");
-
- handle_gbufs(module);
- }
-} EfinixGbufPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/gbuf_map.v b/techlibs/efinix/gbuf_map.v
new file mode 100644
index 000000000..43e0c9ac3
--- /dev/null
+++ b/techlibs/efinix/gbuf_map.v
@@ -0,0 +1,3 @@
+module \$__EFX_GBUF (input I, output O);
+ EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1));
+endmodule
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index d994ae524..001b05945 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -202,7 +202,8 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_gbuf"))
{
- run("efinix_gbuf");
+ run("clkbufmap -buf $__EFX_GBUF O:I");
+ run("techmap -map +/efinix/gbuf_map.v");
run("efinix_fixcarry");
run("clean");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 14:43:11 +0000