diff options
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/synth.cc | 18 | ||||
| -rw-r--r-- | techlibs/ice40/Makefile.inc | 6 | ||||
| -rw-r--r-- | techlibs/ice40/abc_hx.box | 113 | ||||
| -rw-r--r-- | techlibs/ice40/abc_hx.lut | 6 | ||||
| -rw-r--r-- | techlibs/ice40/abc_lp.box | 113 | ||||
| -rw-r--r-- | techlibs/ice40/abc_lp.lut | 6 | ||||
| -rw-r--r-- | techlibs/ice40/abc_u.box | 113 | ||||
| -rw-r--r-- | techlibs/ice40/abc_u.lut | 6 | ||||
| -rw-r--r-- | techlibs/ice40/cells_map.v | 18 | ||||
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 77 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 35 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 86 |
12 files changed, 535 insertions, 62 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index e41c0fe97..ee2e86de9 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -75,13 +75,16 @@ struct SynthPass : public ScriptPass log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); + log(" -abc9\n"); + log(" use abc9 instead of abc\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_module, fsm_opts, memory_opts; + string top_module, fsm_opts, memory_opts, abc; bool autotop, flatten, noalumacc, nofsm, noabc, noshare; int lut; @@ -98,6 +101,7 @@ struct SynthPass : public ScriptPass nofsm = false; noabc = false; noshare = false; + abc = "abc"; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -159,6 +163,10 @@ struct SynthPass : public ScriptPass noshare = true; continue; } + if (args[argidx] == "-abc9") { + abc = "abc9"; + continue; + } break; } extra_args(args, argidx, design); @@ -241,15 +249,15 @@ struct SynthPass : public ScriptPass #ifdef YOSYS_ENABLE_ABC if (help_mode) { - run("abc -fast", " (unless -noabc, unless -lut)"); - run("abc -fast -lut k", "(unless -noabc, if -lut)"); + run(abc + " -fast", " (unless -noabc, unless -lut)"); + run(abc + " -fast -lut k", "(unless -noabc, if -lut)"); } else { if (lut) - run(stringf("abc -fast -lut %d", lut)); + run(stringf("%s -fast -lut %d", abc.c_str(), lut)); else - run("abc -fast"); + run(abc + " -fast"); } run("opt -fast", " (unless -noabc)"); #endif diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 723b59d6f..d258d5a5d 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -28,6 +28,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh)) diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box new file mode 100644 index 000000000..994f3091d --- /dev/null +++ b/techlibs/ice40/abc_hx.box @@ -0,0 +1,113 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt + +# NB: Inputs/Outputs must be ordered alphabetically + +# Inputs: C D +# Outputs: Q +SB_DFF 1 1 2 1 +- - + +# Inputs: C D E +# Outputs: Q +SB_DFFE 2 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFSR 3 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFR 4 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFSS 5 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFS 6 0 3 1 +- - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFESR 7 0 4 1 +- - - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFER 8 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFESS 9 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFES 10 0 4 1 +- - - - + +# Inputs: C D +# Outputs: Q +SB_DFFN 11 0 2 1 +- - + +# Inputs: C D E +# Outputs: Q +SB_DFFNE 12 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFNSR 13 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFNR 14 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFNSS 15 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFNS 16 0 3 1 +- - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFNESR 17 0 4 1 +- - - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFNER 18 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFNESS 19 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFNES 20 0 4 1 +- - - - + +# Inputs: CI I0 I1 +# Outputs: CO +SB_CARRY 21 1 3 1 +126 259 231 + +# Inputs: I0 I1 I2 I3 +# Outputs: O +SB_LUT4 22 0 4 1 +449 400 379 316 diff --git a/techlibs/ice40/abc_hx.lut b/techlibs/ice40/abc_hx.lut new file mode 100644 index 000000000..3b3bb11e2 --- /dev/null +++ b/techlibs/ice40/abc_hx.lut @@ -0,0 +1,6 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt +# I3 I2 I1 I0 +1 1 316 +2 1 316 379 +3 1 316 379 400 +4 1 316 379 400 449 diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box new file mode 100644 index 000000000..002b7bba4 --- /dev/null +++ b/techlibs/ice40/abc_lp.box @@ -0,0 +1,113 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt + +# NB: Inputs/Outputs must be ordered alphabetically + +# Inputs: C D +# Outputs: Q +SB_DFF 1 1 2 1 +- - + +# Inputs: C D E +# Outputs: Q +SB_DFFE 2 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFSR 3 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFR 4 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFSS 5 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFS 6 0 3 1 +- - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFESR 7 0 4 1 +- - - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFER 8 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFESS 9 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFES 10 0 4 1 +- - - - + +# Inputs: C D +# Outputs: Q +SB_DFFN 11 0 2 1 +- - + +# Inputs: C D E +# Outputs: Q +SB_DFFNE 12 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFNSR 13 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFNR 14 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFNSS 15 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFNS 16 0 3 1 +- - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFNESR 17 0 4 1 +- - - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFNER 18 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFNESS 19 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFNES 20 0 4 1 +- - - - + +# Inputs: CI I0 I1 +# Outputs: CO +SB_CARRY 21 1 3 1 +186 675 609 + +# Inputs: I0 I1 I2 I3 +# Outputs: O +SB_LUT4 22 0 4 1 +465 558 589 661 diff --git a/techlibs/ice40/abc_lp.lut b/techlibs/ice40/abc_lp.lut new file mode 100644 index 000000000..e72f760a2 --- /dev/null +++ b/techlibs/ice40/abc_lp.lut @@ -0,0 +1,6 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt +# I3 I2 I1 I0 +1 1 465 +2 1 465 558 +3 1 465 558 589 +4 1 465 558 589 661 diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box new file mode 100644 index 000000000..cb336181c --- /dev/null +++ b/techlibs/ice40/abc_u.box @@ -0,0 +1,113 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt + +# NB: Inputs/Outputs must be ordered alphabetically + +# Inputs: C D +# Outputs: Q +SB_DFF 1 1 2 1 +- - + +# Inputs: C D E +# Outputs: Q +SB_DFFE 2 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFSR 3 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFR 4 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFSS 5 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFS 6 0 3 1 +- - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFESR 7 0 4 1 +- - - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFER 8 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFESS 9 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFES 10 0 4 1 +- - - - + +# Inputs: C D +# Outputs: Q +SB_DFFN 11 0 2 1 +- - + +# Inputs: C D E +# Outputs: Q +SB_DFFNE 12 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFNSR 13 0 3 1 +- - - + +# Inputs: C D R +# Outputs: Q +SB_DFFNR 14 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFNSS 15 0 3 1 +- - - + +# Inputs: C D S +# Outputs: Q +SB_DFFNS 16 0 3 1 +- - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFNESR 17 0 4 1 +- - - - + +# Inputs: C D E R +# Outputs: Q +SB_DFFNER 18 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFNESS 19 0 4 1 +- - - - + +# Inputs: C D E S +# Outputs: Q +SB_DFFNES 20 0 4 1 +- - - - + +# Inputs: CI I0 I1 +# Outputs: CO +SB_CARRY 21 1 3 1 +278 675 609 + +# Inputs: I0 I1 I2 I3 +# Outputs: O +SB_LUT4 22 0 4 1 +1285 1231 1205 874 diff --git a/techlibs/ice40/abc_u.lut b/techlibs/ice40/abc_u.lut new file mode 100644 index 000000000..1e4fcadb6 --- /dev/null +++ b/techlibs/ice40/abc_u.lut @@ -0,0 +1,6 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt +# I3 I2 I1 I0 +1 1 874 +2 1 874 1205 +3 1 874 1205 1231 +4 1 874 1205 1231 1285 diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index d0ddfd02e..287c48b11 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -37,20 +37,24 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin - SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0)); + localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0])); end else if (WIDTH == 2) begin - SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0)); + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}}; + SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0])); end else if (WIDTH == 3) begin - SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0)); + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}}; + SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0])); end else if (WIDTH == 4) begin + localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]}; SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0])); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f9945b2b5..560008bc4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,6 +127,7 @@ endmodule // SiliconBlue Logic Cells +(* abc_box_id = 22 *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -135,24 +136,32 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule +(* abc_box_id = 21, lib_whitebox *) module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule // Positive Edge SiliconBlue FF Cells -module SB_DFF (output `SB_DFF_REG, input C, D); +(* abc_box_id = 1, abc_flop, lib_whitebox *) +module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D); +`ifndef ABC_MODEL always @(posedge C) Q <= D; +`else + always @* Q <= D; +`endif endmodule -module SB_DFFE (output `SB_DFF_REG, input C, E, D); +//(* abc_box_id = 2, abc_flop *) +module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D); always @(posedge C) if (E) Q <= D; endmodule -module SB_DFFSR (output `SB_DFF_REG, input C, R, D); +//(* abc_box_id = 3, abc_flop *) +module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D); always @(posedge C) if (R) Q <= 0; @@ -160,7 +169,8 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D); Q <= D; endmodule -module SB_DFFR (output `SB_DFF_REG, input C, R, D); +//(* abc_box_id = 4, abc_flop *) +module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D); always @(posedge C, posedge R) if (R) Q <= 0; @@ -168,7 +178,8 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D); Q <= D; endmodule -module SB_DFFSS (output `SB_DFF_REG, input C, S, D); +//(* abc_box_id = 5, abc_flop *) +module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D); always @(posedge C) if (S) Q <= 1; @@ -176,7 +187,8 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D); Q <= D; endmodule -module SB_DFFS (output `SB_DFF_REG, input C, S, D); +//(* abc_box_id = 6, abc_flop *) +module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D); always @(posedge C, posedge S) if (S) Q <= 1; @@ -184,7 +196,8 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D); Q <= D; endmodule -module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D); +//(* abc_box_id = 7, abc_flop *) +module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D); always @(posedge C) if (E) begin if (R) @@ -194,7 +207,8 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D); end endmodule -module SB_DFFER (output `SB_DFF_REG, input C, E, R, D); +//(* abc_box_id = 8, abc_flop *) +module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D); always @(posedge C, posedge R) if (R) Q <= 0; @@ -202,7 +216,8 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D); Q <= D; endmodule -module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D); +//(* abc_box_id = 9, abc_flop *) +module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D); always @(posedge C) if (E) begin if (S) @@ -212,7 +227,8 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D); end endmodule -module SB_DFFES (output `SB_DFF_REG, input C, E, S, D); +//(* abc_box_id = 10, abc_flop *) +module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D); always @(posedge C, posedge S) if (S) Q <= 1; @@ -222,18 +238,21 @@ endmodule // Negative Edge SiliconBlue FF Cells -module SB_DFFN (output `SB_DFF_REG, input C, D); +//(* abc_box_id = 11, abc_flop *) +module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D); always @(negedge C) Q <= D; endmodule -module SB_DFFNE (output `SB_DFF_REG, input C, E, D); +//(* abc_box_id = 12, abc_flop *) +module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D); always @(negedge C) if (E) Q <= D; endmodule -module SB_DFFNSR (output `SB_DFF_REG, input C, R, D); +//(* abc_box_id = 13, abc_flop *) +module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D); always @(negedge C) if (R) Q <= 0; @@ -241,7 +260,8 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D); Q <= D; endmodule -module SB_DFFNR (output `SB_DFF_REG, input C, R, D); +//(* abc_box_id = 14, abc_flop *) +module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D); always @(negedge C, posedge R) if (R) Q <= 0; @@ -249,7 +269,8 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D); Q <= D; endmodule -module SB_DFFNSS (output `SB_DFF_REG, input C, S, D); +//(* abc_box_id = 15, abc_flop *) +module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D); always @(negedge C) if (S) Q <= 1; @@ -257,7 +278,8 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D); Q <= D; endmodule -module SB_DFFNS (output `SB_DFF_REG, input C, S, D); +//(* abc_box_id = 16, abc_flop *) +module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D); always @(negedge C, posedge S) if (S) Q <= 1; @@ -265,7 +287,8 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D); Q <= D; endmodule -module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D); +//(* abc_box_id = 17, abc_flop *) +module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D); always @(negedge C) if (E) begin if (R) @@ -275,7 +298,8 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D); end endmodule -module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D); +//(* abc_box_id = 18, abc_flop *) +module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D); always @(negedge C, posedge R) if (R) Q <= 0; @@ -283,7 +307,8 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D); Q <= D; endmodule -module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D); +//(* abc_box_id = 19, abc_flop *) +module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D); always @(negedge C) if (E) begin if (S) @@ -293,7 +318,8 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D); end endmodule -module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D); +//(* abc_box_id = 20, abc_flop *) +module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D); always @(negedge C, posedge S) if (S) Q <= 1; @@ -304,7 +330,7 @@ endmodule // SiliconBlue RAM Cells module SB_RAM40_4K ( - output [15:0] RDATA, + (* abc_flop_q *) output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, input WCLK, WCLKE, WE, @@ -472,7 +498,7 @@ module SB_RAM40_4K ( endmodule module SB_RAM40_4KNR ( - output [15:0] RDATA, + (* abc_flop_q *) output [15:0] RDATA, input RCLKN, RCLKE, RE, input [10:0] RADDR, input WCLK, WCLKE, WE, @@ -537,7 +563,7 @@ module SB_RAM40_4KNR ( endmodule module SB_RAM40_4KNW ( - output [15:0] RDATA, + (* abc_flop_q *) output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, input WCLKN, WCLKE, WE, @@ -602,7 +628,7 @@ module SB_RAM40_4KNW ( endmodule module SB_RAM40_4KNRNW ( - output [15:0] RDATA, + (* abc_flop_q *) output [15:0] RDATA, input RCLKN, RCLKE, RE, input [10:0] RADDR, input WCLKN, WCLKE, WE, @@ -890,12 +916,13 @@ module SB_WARMBOOT ( ); endmodule +(* nomem2reg *) module SB_SPRAM256KA ( input [13:0] ADDRESS, input [15:0] DATAIN, input [3:0] MASKWREN, input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF, - output reg [15:0] DATAOUT + (* abc_flop_q *) output reg [15:0] DATAOUT ); `ifndef BLACKBOX `ifndef EQUIV diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index bb96d66d1..168161a90 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass log("\n"); log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); + log(" -device < hx | lp | u >\n"); + log(" optimise the synthesis netlist for the specified device.\n"); + log(" HX is the default target if no device argument specified.\n"); + log("\n"); log(" -top <module>\n"); log(" use the specified module as top module\n"); log("\n"); @@ -92,13 +96,17 @@ struct SynthIce40Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -abc9\n"); + log(" use abc9 instead of abc\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, blif_file, edif_file, json_file; + + string top_opt, blif_file, edif_file, json_file, abc, device_opt; bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr; int min_ce_use; @@ -119,6 +127,8 @@ struct SynthIce40Pass : public ScriptPass noabc = false; abc2 = false; vpr = false; + abc = "abc"; + device_opt = "hx"; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -201,12 +211,22 @@ struct SynthIce40Pass : public ScriptPass vpr = true; continue; } + if (args[argidx] == "-abc9") { + abc = "abc9"; + continue; + } + if (args[argidx] == "-device" && argidx+1 < args.size()) { + device_opt = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") + log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str()); log_header(design, "Executing SYNTH_ICE40 pass.\n"); log_push(); @@ -220,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib +/ice40/cells_sim.v"); + run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -277,8 +297,8 @@ struct SynthIce40Pass : public ScriptPass run("techmap"); else run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); - if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + if ((retime || help_mode) && abc != "abc9") + run(abc + " -dff", "(only if -retime)"); run("ice40_opt"); } @@ -302,7 +322,7 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_luts")) { if (abc2 || help_mode) { - run("abc", " (only if -abc2)"); + run(abc, " (only if -abc2)"); run("ice40_opt", "(only if -abc2)"); } run("techmap -map +/ice40/latches_map.v"); @@ -311,7 +331,10 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); } if (!noabc) { - run("abc -dress -lut 4", "(skip if -noabc)"); + if (abc == "abc9") + run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + else + run(abc + " -lut 4", "(skip if -noabc)"); } run("clean"); if (relut || help_mode) { diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a293081f1..f966115cd 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -58,6 +58,9 @@ struct SynthXilinxPass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -nocarry\n"); + log(" disable inference of carry chains\n"); + log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); log("\n"); @@ -67,6 +70,9 @@ struct SynthXilinxPass : public ScriptPass log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); + log(" -nomux\n"); + log(" disable inference of wide multiplexers\n"); + log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -78,26 +84,32 @@ struct SynthXilinxPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -abc9\n"); + log(" use abc9 instead of abc\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - std::string top_opt, edif_file, blif_file, arch; - bool flatten, retime, vpr, nobram, nodram, nosrl; + std::string top_opt, edif_file, blif_file, abc, arch; + bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux; void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; edif_file.clear(); blif_file.clear(); + abc = "abc"; flatten = false; retime = false; vpr = false; + nocarry = false; nobram = false; nodram = false; nosrl = false; + nomux = false; arch = "xc7"; } @@ -145,6 +157,10 @@ struct SynthXilinxPass : public ScriptPass vpr = true; continue; } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -157,6 +173,14 @@ struct SynthXilinxPass : public ScriptPass nosrl = true; continue; } + if (args[argidx] == "-nomux") { + nomux = true; + continue; + } + if (args[argidx] == "-abc9") { + abc = "abc9"; + continue; + } break; } extra_args(args, argidx, design); @@ -179,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass { if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib +/xilinx/cells_sim.v"); + run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v"); run("read_verilog -lib +/xilinx/cells_xtra.v"); @@ -200,6 +224,21 @@ struct SynthXilinxPass : public ScriptPass if (check_label("coarse")) { run("synth -run coarse"); + + //if (!nomux || help_mode) + // run("muxpack", "(skip if '-nomux')"); + + // shregmap -tech xilinx can cope with $shiftx and $mux + // cells for identifying variable-length shift registers, + // so attempt to convert $pmux-es to the former + // Also: wide multiplexer inference benefits from this too + if (!(nosrl && nomux) || help_mode) + run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); + + // Run a number of peephole optimisations, including one + // that optimises $mul cells driving $shiftx's B input + // and that aids wide mux analysis + run("peepopt"); } if (check_label("bram", "(skip if '-nobram')")) { @@ -217,12 +256,6 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("fine")) { - // shregmap -tech xilinx can cope with $shiftx and $mux - // cells for identifiying variable-length shift registers, - // so attempt to convert $pmux-es to the former - if (!nosrl || help_mode) - run("pmux2shiftx", "(skip if '-nosrl')"); - run("opt -fast -full"); run("memory_map"); run("dffsr2dff"); @@ -237,30 +270,45 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - if (!vpr || help_mode) - run("techmap -map +/techmap.v -map +/xilinx/arith_map.v"); - else - run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - + std::string techmap_files = " -map +/techmap.v"; + if (help_mode) + techmap_files += " [-map +/xilinx/mux_map.v]"; + else if (!nomux) + techmap_files += " -map +/xilinx/mux_map.v"; + if (help_mode) + techmap_files += " [-map +/xilinx/arith_map.v]"; + else if (!nocarry) { + techmap_files += " -map +/xilinx/arith_map.v"; + if (vpr) + techmap_files += " -D _EXPLICIT_CARRY"; + else if (abc == "abc9") + techmap_files += " -D _CLB_CARRY"; + } + run("techmap " + techmap_files); run("opt -fast"); } if (check_label("map_cells")) { + if (!nomux || help_mode) + run("muxcover -mux8 -mux16", "(skip if '-nomux')"); run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("clean"); } if (check_label("map_luts")) { - if (help_mode) - run("abc -luts 2:2,3,6:5,10,20 [-dff]"); + if (abc == "abc9") + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); + else if (help_mode) + run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else - run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run("clean"); + // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); |